haru/stm32f401ccu6-dma-gpio
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stm32f401ccu6-dma-gpio/Debug/f401dmagpio.list
haru 0652542602 initial
2022-10-24 13:12:10 +09:00

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f401dmagpio.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000194 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002a80 08000194 08000194 00010194 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000028 08002c14 08002c14 00012c14 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002c3c 08002c3c 0002000c 2**0
CONTENTS
4 .ARM 00000008 08002c3c 08002c3c 00012c3c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08002c44 08002c44 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002c44 08002c44 00012c44 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002c48 08002c48 00012c48 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002c4c 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000b0 2000000c 08002c58 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 200000bc 08002c58 000200bc 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00009682 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000163e 00000000 00000000 000296be 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000978 00000000 00000000 0002ad00 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 000008d0 00000000 00000000 0002b678 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00014eeb 00000000 00000000 0002bf48 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009add 00000000 00000000 00040e33 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00086b61 00000000 00000000 0004a910 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000d1471 2**0
CONTENTS, READONLY
20 .debug_frame 00002764 00000000 00000000 000d14c4 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000194 <__do_global_dtors_aux>:
8000194: b510 push {r4, lr}
8000196: 4c05 ldr r4, [pc, #20] ; (80001ac <__do_global_dtors_aux+0x18>)
8000198: 7823 ldrb r3, [r4, #0]
800019a: b933 cbnz r3, 80001aa <__do_global_dtors_aux+0x16>
800019c: 4b04 ldr r3, [pc, #16] ; (80001b0 <__do_global_dtors_aux+0x1c>)
800019e: b113 cbz r3, 80001a6 <__do_global_dtors_aux+0x12>
80001a0: 4804 ldr r0, [pc, #16] ; (80001b4 <__do_global_dtors_aux+0x20>)
80001a2: f3af 8000 nop.w
80001a6: 2301 movs r3, #1
80001a8: 7023 strb r3, [r4, #0]
80001aa: bd10 pop {r4, pc}
80001ac: 2000000c .word 0x2000000c
80001b0: 00000000 .word 0x00000000
80001b4: 08002bfc .word 0x08002bfc
080001b8 <frame_dummy>:
80001b8: b508 push {r3, lr}
80001ba: 4b03 ldr r3, [pc, #12] ; (80001c8 <frame_dummy+0x10>)
80001bc: b11b cbz r3, 80001c6 <frame_dummy+0xe>
80001be: 4903 ldr r1, [pc, #12] ; (80001cc <frame_dummy+0x14>)
80001c0: 4803 ldr r0, [pc, #12] ; (80001d0 <frame_dummy+0x18>)
80001c2: f3af 8000 nop.w
80001c6: bd08 pop {r3, pc}
80001c8: 00000000 .word 0x00000000
80001cc: 20000010 .word 0x20000010
80001d0: 08002bfc .word 0x08002bfc
080001d4 <__aeabi_uldivmod>:
80001d4: b953 cbnz r3, 80001ec <__aeabi_uldivmod+0x18>
80001d6: b94a cbnz r2, 80001ec <__aeabi_uldivmod+0x18>
80001d8: 2900 cmp r1, #0
80001da: bf08 it eq
80001dc: 2800 cmpeq r0, #0
80001de: bf1c itt ne
80001e0: f04f 31ff movne.w r1, #4294967295
80001e4: f04f 30ff movne.w r0, #4294967295
80001e8: f000 b974 b.w 80004d4 <__aeabi_idiv0>
80001ec: f1ad 0c08 sub.w ip, sp, #8
80001f0: e96d ce04 strd ip, lr, [sp, #-16]!
80001f4: f000 f806 bl 8000204 <__udivmoddi4>
80001f8: f8dd e004 ldr.w lr, [sp, #4]
80001fc: e9dd 2302 ldrd r2, r3, [sp, #8]
8000200: b004 add sp, #16
8000202: 4770 bx lr
08000204 <__udivmoddi4>:
8000204: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000208: 9d08 ldr r5, [sp, #32]
800020a: 4604 mov r4, r0
800020c: 468e mov lr, r1
800020e: 2b00 cmp r3, #0
8000210: d14d bne.n 80002ae <__udivmoddi4+0xaa>
8000212: 428a cmp r2, r1
8000214: 4694 mov ip, r2
8000216: d969 bls.n 80002ec <__udivmoddi4+0xe8>
8000218: fab2 f282 clz r2, r2
800021c: b152 cbz r2, 8000234 <__udivmoddi4+0x30>
800021e: fa01 f302 lsl.w r3, r1, r2
8000222: f1c2 0120 rsb r1, r2, #32
8000226: fa20 f101 lsr.w r1, r0, r1
800022a: fa0c fc02 lsl.w ip, ip, r2
800022e: ea41 0e03 orr.w lr, r1, r3
8000232: 4094 lsls r4, r2
8000234: ea4f 481c mov.w r8, ip, lsr #16
8000238: 0c21 lsrs r1, r4, #16
800023a: fbbe f6f8 udiv r6, lr, r8
800023e: fa1f f78c uxth.w r7, ip
8000242: fb08 e316 mls r3, r8, r6, lr
8000246: ea41 4303 orr.w r3, r1, r3, lsl #16
800024a: fb06 f107 mul.w r1, r6, r7
800024e: 4299 cmp r1, r3
8000250: d90a bls.n 8000268 <__udivmoddi4+0x64>
8000252: eb1c 0303 adds.w r3, ip, r3
8000256: f106 30ff add.w r0, r6, #4294967295
800025a: f080 811f bcs.w 800049c <__udivmoddi4+0x298>
800025e: 4299 cmp r1, r3
8000260: f240 811c bls.w 800049c <__udivmoddi4+0x298>
8000264: 3e02 subs r6, #2
8000266: 4463 add r3, ip
8000268: 1a5b subs r3, r3, r1
800026a: b2a4 uxth r4, r4
800026c: fbb3 f0f8 udiv r0, r3, r8
8000270: fb08 3310 mls r3, r8, r0, r3
8000274: ea44 4403 orr.w r4, r4, r3, lsl #16
8000278: fb00 f707 mul.w r7, r0, r7
800027c: 42a7 cmp r7, r4
800027e: d90a bls.n 8000296 <__udivmoddi4+0x92>
8000280: eb1c 0404 adds.w r4, ip, r4
8000284: f100 33ff add.w r3, r0, #4294967295
8000288: f080 810a bcs.w 80004a0 <__udivmoddi4+0x29c>
800028c: 42a7 cmp r7, r4
800028e: f240 8107 bls.w 80004a0 <__udivmoddi4+0x29c>
8000292: 4464 add r4, ip
8000294: 3802 subs r0, #2
8000296: ea40 4006 orr.w r0, r0, r6, lsl #16
800029a: 1be4 subs r4, r4, r7
800029c: 2600 movs r6, #0
800029e: b11d cbz r5, 80002a8 <__udivmoddi4+0xa4>
80002a0: 40d4 lsrs r4, r2
80002a2: 2300 movs r3, #0
80002a4: e9c5 4300 strd r4, r3, [r5]
80002a8: 4631 mov r1, r6
80002aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ae: 428b cmp r3, r1
80002b0: d909 bls.n 80002c6 <__udivmoddi4+0xc2>
80002b2: 2d00 cmp r5, #0
80002b4: f000 80ef beq.w 8000496 <__udivmoddi4+0x292>
80002b8: 2600 movs r6, #0
80002ba: e9c5 0100 strd r0, r1, [r5]
80002be: 4630 mov r0, r6
80002c0: 4631 mov r1, r6
80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c6: fab3 f683 clz r6, r3
80002ca: 2e00 cmp r6, #0
80002cc: d14a bne.n 8000364 <__udivmoddi4+0x160>
80002ce: 428b cmp r3, r1
80002d0: d302 bcc.n 80002d8 <__udivmoddi4+0xd4>
80002d2: 4282 cmp r2, r0
80002d4: f200 80f9 bhi.w 80004ca <__udivmoddi4+0x2c6>
80002d8: 1a84 subs r4, r0, r2
80002da: eb61 0303 sbc.w r3, r1, r3
80002de: 2001 movs r0, #1
80002e0: 469e mov lr, r3
80002e2: 2d00 cmp r5, #0
80002e4: d0e0 beq.n 80002a8 <__udivmoddi4+0xa4>
80002e6: e9c5 4e00 strd r4, lr, [r5]
80002ea: e7dd b.n 80002a8 <__udivmoddi4+0xa4>
80002ec: b902 cbnz r2, 80002f0 <__udivmoddi4+0xec>
80002ee: deff udf #255 ; 0xff
80002f0: fab2 f282 clz r2, r2
80002f4: 2a00 cmp r2, #0
80002f6: f040 8092 bne.w 800041e <__udivmoddi4+0x21a>
80002fa: eba1 010c sub.w r1, r1, ip
80002fe: ea4f 471c mov.w r7, ip, lsr #16
8000302: fa1f fe8c uxth.w lr, ip
8000306: 2601 movs r6, #1
8000308: 0c20 lsrs r0, r4, #16
800030a: fbb1 f3f7 udiv r3, r1, r7
800030e: fb07 1113 mls r1, r7, r3, r1
8000312: ea40 4101 orr.w r1, r0, r1, lsl #16
8000316: fb0e f003 mul.w r0, lr, r3
800031a: 4288 cmp r0, r1
800031c: d908 bls.n 8000330 <__udivmoddi4+0x12c>
800031e: eb1c 0101 adds.w r1, ip, r1
8000322: f103 38ff add.w r8, r3, #4294967295
8000326: d202 bcs.n 800032e <__udivmoddi4+0x12a>
8000328: 4288 cmp r0, r1
800032a: f200 80cb bhi.w 80004c4 <__udivmoddi4+0x2c0>
800032e: 4643 mov r3, r8
8000330: 1a09 subs r1, r1, r0
8000332: b2a4 uxth r4, r4
8000334: fbb1 f0f7 udiv r0, r1, r7
8000338: fb07 1110 mls r1, r7, r0, r1
800033c: ea44 4401 orr.w r4, r4, r1, lsl #16
8000340: fb0e fe00 mul.w lr, lr, r0
8000344: 45a6 cmp lr, r4
8000346: d908 bls.n 800035a <__udivmoddi4+0x156>
8000348: eb1c 0404 adds.w r4, ip, r4
800034c: f100 31ff add.w r1, r0, #4294967295
8000350: d202 bcs.n 8000358 <__udivmoddi4+0x154>
8000352: 45a6 cmp lr, r4
8000354: f200 80bb bhi.w 80004ce <__udivmoddi4+0x2ca>
8000358: 4608 mov r0, r1
800035a: eba4 040e sub.w r4, r4, lr
800035e: ea40 4003 orr.w r0, r0, r3, lsl #16
8000362: e79c b.n 800029e <__udivmoddi4+0x9a>
8000364: f1c6 0720 rsb r7, r6, #32
8000368: 40b3 lsls r3, r6
800036a: fa22 fc07 lsr.w ip, r2, r7
800036e: ea4c 0c03 orr.w ip, ip, r3
8000372: fa20 f407 lsr.w r4, r0, r7
8000376: fa01 f306 lsl.w r3, r1, r6
800037a: 431c orrs r4, r3
800037c: 40f9 lsrs r1, r7
800037e: ea4f 491c mov.w r9, ip, lsr #16
8000382: fa00 f306 lsl.w r3, r0, r6
8000386: fbb1 f8f9 udiv r8, r1, r9
800038a: 0c20 lsrs r0, r4, #16
800038c: fa1f fe8c uxth.w lr, ip
8000390: fb09 1118 mls r1, r9, r8, r1
8000394: ea40 4101 orr.w r1, r0, r1, lsl #16
8000398: fb08 f00e mul.w r0, r8, lr
800039c: 4288 cmp r0, r1
800039e: fa02 f206 lsl.w r2, r2, r6
80003a2: d90b bls.n 80003bc <__udivmoddi4+0x1b8>
80003a4: eb1c 0101 adds.w r1, ip, r1
80003a8: f108 3aff add.w sl, r8, #4294967295
80003ac: f080 8088 bcs.w 80004c0 <__udivmoddi4+0x2bc>
80003b0: 4288 cmp r0, r1
80003b2: f240 8085 bls.w 80004c0 <__udivmoddi4+0x2bc>
80003b6: f1a8 0802 sub.w r8, r8, #2
80003ba: 4461 add r1, ip
80003bc: 1a09 subs r1, r1, r0
80003be: b2a4 uxth r4, r4
80003c0: fbb1 f0f9 udiv r0, r1, r9
80003c4: fb09 1110 mls r1, r9, r0, r1
80003c8: ea44 4101 orr.w r1, r4, r1, lsl #16
80003cc: fb00 fe0e mul.w lr, r0, lr
80003d0: 458e cmp lr, r1
80003d2: d908 bls.n 80003e6 <__udivmoddi4+0x1e2>
80003d4: eb1c 0101 adds.w r1, ip, r1
80003d8: f100 34ff add.w r4, r0, #4294967295
80003dc: d26c bcs.n 80004b8 <__udivmoddi4+0x2b4>
80003de: 458e cmp lr, r1
80003e0: d96a bls.n 80004b8 <__udivmoddi4+0x2b4>
80003e2: 3802 subs r0, #2
80003e4: 4461 add r1, ip
80003e6: ea40 4008 orr.w r0, r0, r8, lsl #16
80003ea: fba0 9402 umull r9, r4, r0, r2
80003ee: eba1 010e sub.w r1, r1, lr
80003f2: 42a1 cmp r1, r4
80003f4: 46c8 mov r8, r9
80003f6: 46a6 mov lr, r4
80003f8: d356 bcc.n 80004a8 <__udivmoddi4+0x2a4>
80003fa: d053 beq.n 80004a4 <__udivmoddi4+0x2a0>
80003fc: b15d cbz r5, 8000416 <__udivmoddi4+0x212>
80003fe: ebb3 0208 subs.w r2, r3, r8
8000402: eb61 010e sbc.w r1, r1, lr
8000406: fa01 f707 lsl.w r7, r1, r7
800040a: fa22 f306 lsr.w r3, r2, r6
800040e: 40f1 lsrs r1, r6
8000410: 431f orrs r7, r3
8000412: e9c5 7100 strd r7, r1, [r5]
8000416: 2600 movs r6, #0
8000418: 4631 mov r1, r6
800041a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800041e: f1c2 0320 rsb r3, r2, #32
8000422: 40d8 lsrs r0, r3
8000424: fa0c fc02 lsl.w ip, ip, r2
8000428: fa21 f303 lsr.w r3, r1, r3
800042c: 4091 lsls r1, r2
800042e: 4301 orrs r1, r0
8000430: ea4f 471c mov.w r7, ip, lsr #16
8000434: fa1f fe8c uxth.w lr, ip
8000438: fbb3 f0f7 udiv r0, r3, r7
800043c: fb07 3610 mls r6, r7, r0, r3
8000440: 0c0b lsrs r3, r1, #16
8000442: ea43 4306 orr.w r3, r3, r6, lsl #16
8000446: fb00 f60e mul.w r6, r0, lr
800044a: 429e cmp r6, r3
800044c: fa04 f402 lsl.w r4, r4, r2
8000450: d908 bls.n 8000464 <__udivmoddi4+0x260>
8000452: eb1c 0303 adds.w r3, ip, r3
8000456: f100 38ff add.w r8, r0, #4294967295
800045a: d22f bcs.n 80004bc <__udivmoddi4+0x2b8>
800045c: 429e cmp r6, r3
800045e: d92d bls.n 80004bc <__udivmoddi4+0x2b8>
8000460: 3802 subs r0, #2
8000462: 4463 add r3, ip
8000464: 1b9b subs r3, r3, r6
8000466: b289 uxth r1, r1
8000468: fbb3 f6f7 udiv r6, r3, r7
800046c: fb07 3316 mls r3, r7, r6, r3
8000470: ea41 4103 orr.w r1, r1, r3, lsl #16
8000474: fb06 f30e mul.w r3, r6, lr
8000478: 428b cmp r3, r1
800047a: d908 bls.n 800048e <__udivmoddi4+0x28a>
800047c: eb1c 0101 adds.w r1, ip, r1
8000480: f106 38ff add.w r8, r6, #4294967295
8000484: d216 bcs.n 80004b4 <__udivmoddi4+0x2b0>
8000486: 428b cmp r3, r1
8000488: d914 bls.n 80004b4 <__udivmoddi4+0x2b0>
800048a: 3e02 subs r6, #2
800048c: 4461 add r1, ip
800048e: 1ac9 subs r1, r1, r3
8000490: ea46 4600 orr.w r6, r6, r0, lsl #16
8000494: e738 b.n 8000308 <__udivmoddi4+0x104>
8000496: 462e mov r6, r5
8000498: 4628 mov r0, r5
800049a: e705 b.n 80002a8 <__udivmoddi4+0xa4>
800049c: 4606 mov r6, r0
800049e: e6e3 b.n 8000268 <__udivmoddi4+0x64>
80004a0: 4618 mov r0, r3
80004a2: e6f8 b.n 8000296 <__udivmoddi4+0x92>
80004a4: 454b cmp r3, r9
80004a6: d2a9 bcs.n 80003fc <__udivmoddi4+0x1f8>
80004a8: ebb9 0802 subs.w r8, r9, r2
80004ac: eb64 0e0c sbc.w lr, r4, ip
80004b0: 3801 subs r0, #1
80004b2: e7a3 b.n 80003fc <__udivmoddi4+0x1f8>
80004b4: 4646 mov r6, r8
80004b6: e7ea b.n 800048e <__udivmoddi4+0x28a>
80004b8: 4620 mov r0, r4
80004ba: e794 b.n 80003e6 <__udivmoddi4+0x1e2>
80004bc: 4640 mov r0, r8
80004be: e7d1 b.n 8000464 <__udivmoddi4+0x260>
80004c0: 46d0 mov r8, sl
80004c2: e77b b.n 80003bc <__udivmoddi4+0x1b8>
80004c4: 3b02 subs r3, #2
80004c6: 4461 add r1, ip
80004c8: e732 b.n 8000330 <__udivmoddi4+0x12c>
80004ca: 4630 mov r0, r6
80004cc: e709 b.n 80002e2 <__udivmoddi4+0xde>
80004ce: 4464 add r4, ip
80004d0: 3802 subs r0, #2
80004d2: e742 b.n 800035a <__udivmoddi4+0x156>
080004d4 <__aeabi_idiv0>:
80004d4: 4770 bx lr
80004d6: bf00 nop
080004d8 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80004d8: b480 push {r7}
80004da: b083 sub sp, #12
80004dc: af00 add r7, sp, #0
80004de: 4603 mov r3, r0
80004e0: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80004e2: f997 3007 ldrsb.w r3, [r7, #7]
80004e6: 2b00 cmp r3, #0
80004e8: db0b blt.n 8000502 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80004ea: 79fb ldrb r3, [r7, #7]
80004ec: f003 021f and.w r2, r3, #31
80004f0: 4907 ldr r1, [pc, #28] ; (8000510 <__NVIC_EnableIRQ+0x38>)
80004f2: f997 3007 ldrsb.w r3, [r7, #7]
80004f6: 095b lsrs r3, r3, #5
80004f8: 2001 movs r0, #1
80004fa: fa00 f202 lsl.w r2, r0, r2
80004fe: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000502: bf00 nop
8000504: 370c adds r7, #12
8000506: 46bd mov sp, r7
8000508: f85d 7b04 ldr.w r7, [sp], #4
800050c: 4770 bx lr
800050e: bf00 nop
8000510: e000e100 .word 0xe000e100
08000514 <DMA2_Stream6_IRQHandler>:
// TIM1->CR1 &= ~(TIM_CR1_CEN);
// }
//}
//HISR(Stream4~Stream7)
void DMA2_Stream6_IRQHandler(){
8000514: b480 push {r7}
8000516: af00 add r7, sp, #0
if(DMA2->HISR & DMA_HISR_TCIF6){
8000518: 4b15 ldr r3, [pc, #84] ; (8000570 <DMA2_Stream6_IRQHandler+0x5c>)
800051a: 685b ldr r3, [r3, #4]
800051c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000520: 2b00 cmp r3, #0
8000522: d01f beq.n 8000564 <DMA2_Stream6_IRQHandler+0x50>
DMA2->HIFCR |= DMA_HIFCR_CTCIF6;
8000524: 4b12 ldr r3, [pc, #72] ; (8000570 <DMA2_Stream6_IRQHandler+0x5c>)
8000526: 68db ldr r3, [r3, #12]
8000528: 4a11 ldr r2, [pc, #68] ; (8000570 <DMA2_Stream6_IRQHandler+0x5c>)
800052a: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
800052e: 60d3 str r3, [r2, #12]
TIM1->BDTR &= ~(TIM_BDTR_MOE);
8000530: 4b10 ldr r3, [pc, #64] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
8000532: 6c5b ldr r3, [r3, #68] ; 0x44
8000534: 4a0f ldr r2, [pc, #60] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
8000536: f423 4300 bic.w r3, r3, #32768 ; 0x8000
800053a: 6453 str r3, [r2, #68] ; 0x44
TIM1->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E);
800053c: 4b0d ldr r3, [pc, #52] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
800053e: 6a1b ldr r3, [r3, #32]
8000540: 4a0c ldr r2, [pc, #48] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
8000542: f423 7388 bic.w r3, r3, #272 ; 0x110
8000546: f023 0301 bic.w r3, r3, #1
800054a: 6213 str r3, [r2, #32]
TIM1->CR1 &= ~(TIM_CR1_CEN);
800054c: 4b09 ldr r3, [pc, #36] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
800054e: 681b ldr r3, [r3, #0]
8000550: 4a08 ldr r2, [pc, #32] ; (8000574 <DMA2_Stream6_IRQHandler+0x60>)
8000552: f023 0301 bic.w r3, r3, #1
8000556: 6013 str r3, [r2, #0]
GPIOA->BSRR = 0xff;
8000558: 4b07 ldr r3, [pc, #28] ; (8000578 <DMA2_Stream6_IRQHandler+0x64>)
800055a: 22ff movs r2, #255 ; 0xff
800055c: 619a str r2, [r3, #24]
GPIOB->BSRR = 0xff;
800055e: 4b07 ldr r3, [pc, #28] ; (800057c <DMA2_Stream6_IRQHandler+0x68>)
8000560: 22ff movs r2, #255 ; 0xff
8000562: 619a str r2, [r3, #24]
}
}
8000564: bf00 nop
8000566: 46bd mov sp, r7
8000568: f85d 7b04 ldr.w r7, [sp], #4
800056c: 4770 bx lr
800056e: bf00 nop
8000570: 40026400 .word 0x40026400
8000574: 40010000 .word 0x40010000
8000578: 40020000 .word 0x40020000
800057c: 40020400 .word 0x40020400
08000580 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000580: b5b0 push {r4, r5, r7, lr}
8000582: b086 sub sp, #24
8000584: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000586: f000 fbb9 bl 8000cfc <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800058a: f000 f87f bl 800068c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800058e: f000 f9df bl 8000950 <MX_GPIO_Init>
MX_TIM11_Init();
8000592: f000 f9b9 bl 8000908 <MX_TIM11_Init>
MX_TIM1_Init();
8000596: f000 f8e3 bl 8000760 <MX_TIM1_Init>
/* USER CODE BEGIN 2 */
__NVIC_EnableIRQ(DMA2_Stream6_IRQn); //Enable Interrupt
800059a: 2045 movs r0, #69 ; 0x45
800059c: f7ff ff9c bl 80004d8 <__NVIC_EnableIRQ>
HAL_TIM_Base_Start_IT(&htim11);
80005a0: 482f ldr r0, [pc, #188] ; (8000660 <main+0xe0>)
80005a2: f001 fb5b bl 8001c5c <HAL_TIM_Base_Start_IT>
*(uint8_t*)(&GPIOA->ODR) = 0xff;
80005a6: 4b2f ldr r3, [pc, #188] ; (8000664 <main+0xe4>)
80005a8: 22ff movs r2, #255 ; 0xff
80005aa: 701a strb r2, [r3, #0]
*(uint8_t*)(&GPIOB->ODR) = 0xff;
80005ac: 4b2e ldr r3, [pc, #184] ; (8000668 <main+0xe8>)
80005ae: 22ff movs r2, #255 ; 0xff
80005b0: 701a strb r2, [r3, #0]
uint8_t data[] = {0x55,0xaa,0x00,0xff,0x55,0xaa,0x00,0xff,0x55,0xaa,0x00,0xff,0x55,0xaa,0x00,0xff,0x55,0xaa,0x00,0xff,0x55,0xaa,0x00,0xff};
80005b2: 4b2e ldr r3, [pc, #184] ; (800066c <main+0xec>)
80005b4: 463c mov r4, r7
80005b6: 461d mov r5, r3
80005b8: cd0f ldmia r5!, {r0, r1, r2, r3}
80005ba: c40f stmia r4!, {r0, r1, r2, r3}
80005bc: e895 0003 ldmia.w r5, {r0, r1}
80005c0: e884 0003 stmia.w r4, {r0, r1}
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; //DMA2 enable
80005c4: 4b2a ldr r3, [pc, #168] ; (8000670 <main+0xf0>)
80005c6: 6b1b ldr r3, [r3, #48] ; 0x30
80005c8: 4a29 ldr r2, [pc, #164] ; (8000670 <main+0xf0>)
80005ca: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
80005ce: 6313 str r3, [r2, #48] ; 0x30
GPIOA->BSRR = 0x100; //Set clock pin to SET.
80005d0: 4b28 ldr r3, [pc, #160] ; (8000674 <main+0xf4>)
80005d2: f44f 7280 mov.w r2, #256 ; 0x100
80005d6: 619a str r2, [r3, #24]
// DMA_SxCR_MINC |
// DMA_SxCR_DIR_0 |
// DMA_SxCR_EN;
//TIM1_CH3 @ DMA2/Stream6/CH6
DMA2_Stream6->NDTR = 16;
80005d8: 4b27 ldr r3, [pc, #156] ; (8000678 <main+0xf8>)
80005da: 2210 movs r2, #16
80005dc: 605a str r2, [r3, #4]
DMA2_Stream6->M0AR = (uint32_t)data;
80005de: 4a26 ldr r2, [pc, #152] ; (8000678 <main+0xf8>)
80005e0: 463b mov r3, r7
80005e2: 60d3 str r3, [r2, #12]
*(uint8_t*)(&GPIOA->ODR) = 0;
80005e4: 4b1f ldr r3, [pc, #124] ; (8000664 <main+0xe4>)
80005e6: 2200 movs r2, #0
80005e8: 701a strb r2, [r3, #0]
DMA2_Stream6->PAR = (uint32_t)&GPIOA->ODR;
80005ea: 4b23 ldr r3, [pc, #140] ; (8000678 <main+0xf8>)
80005ec: 4a1d ldr r2, [pc, #116] ; (8000664 <main+0xe4>)
80005ee: 609a str r2, [r3, #8]
DMA2_Stream6->CR = (6u << DMA_SxCR_CHSEL_Pos) | //CH6
80005f0: 4b21 ldr r3, [pc, #132] ; (8000678 <main+0xf8>)
80005f2: 4a22 ldr r2, [pc, #136] ; (800067c <main+0xfc>)
80005f4: 601a str r2, [r3, #0]
DMA_SxCR_DIR_0 | //Memory to Peripheral
DMA_IT_TC | //Transmission Complete Interrupt
DMA_SxCR_EN; //Stream Enable
//TIM1_CH2 @ DMA2/Stream2/CH6
DMA2_Stream2->NDTR = 16;
80005f6: 4b22 ldr r3, [pc, #136] ; (8000680 <main+0x100>)
80005f8: 2210 movs r2, #16
80005fa: 605a str r2, [r3, #4]
DMA2_Stream2->M0AR = (uint32_t)(data+1);
80005fc: 463b mov r3, r7
80005fe: 3301 adds r3, #1
8000600: 4a1f ldr r2, [pc, #124] ; (8000680 <main+0x100>)
8000602: 60d3 str r3, [r2, #12]
*(uint8_t*)(&GPIOB->ODR) = 0;
8000604: 4b18 ldr r3, [pc, #96] ; (8000668 <main+0xe8>)
8000606: 2200 movs r2, #0
8000608: 701a strb r2, [r3, #0]
DMA2_Stream2->PAR = (uint32_t)&GPIOB->ODR;
800060a: 4b1d ldr r3, [pc, #116] ; (8000680 <main+0x100>)
800060c: 4a16 ldr r2, [pc, #88] ; (8000668 <main+0xe8>)
800060e: 609a str r2, [r3, #8]
DMA2_Stream2->CR = (6u << DMA_SxCR_CHSEL_Pos) |
8000610: 4b1b ldr r3, [pc, #108] ; (8000680 <main+0x100>)
8000612: 4a1c ldr r2, [pc, #112] ; (8000684 <main+0x104>)
8000614: 601a str r2, [r3, #0]
DMA_SxCR_MINC |
DMA_SxCR_DIR_0 |
DMA_SxCR_EN;
TIM1->PSC = 0;
8000616: 4b1c ldr r3, [pc, #112] ; (8000688 <main+0x108>)
8000618: 2200 movs r2, #0
800061a: 629a str r2, [r3, #40] ; 0x28
TIM1->ARR = 83; //1MHz for DMA clock
800061c: 4b1a ldr r3, [pc, #104] ; (8000688 <main+0x108>)
800061e: 2253 movs r2, #83 ; 0x53
8000620: 62da str r2, [r3, #44] ; 0x2c
TIM1->DIER = TIM_DIER_CC2DE | TIM_DIER_CC3DE; //Enable interrupts. (add TIM_DIER_UDE for TIMx_UP.)
8000622: 4b19 ldr r3, [pc, #100] ; (8000688 <main+0x108>)
8000624: f44f 6240 mov.w r2, #3072 ; 0xc00
8000628: 60da str r2, [r3, #12]
TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E; //Capture compare enable. used for PWM and OC.
800062a: 4b17 ldr r3, [pc, #92] ; (8000688 <main+0x108>)
800062c: f240 1211 movw r2, #273 ; 0x111
8000630: 621a str r2, [r3, #32]
TIM1->CCR1 = 41; //About half for clock output timing.
8000632: 4b15 ldr r3, [pc, #84] ; (8000688 <main+0x108>)
8000634: 2229 movs r2, #41 ; 0x29
8000636: 635a str r2, [r3, #52] ; 0x34
TIM1->CCR2 = 0; //Start immediately for DMA transfer when timer starts.
8000638: 4b13 ldr r3, [pc, #76] ; (8000688 <main+0x108>)
800063a: 2200 movs r2, #0
800063c: 639a str r2, [r3, #56] ; 0x38
TIM1->CCR3 = 0; //same
800063e: 4b12 ldr r3, [pc, #72] ; (8000688 <main+0x108>)
8000640: 2200 movs r2, #0
8000642: 63da str r2, [r3, #60] ; 0x3c
TIM1->CNT = TIM1->ARR - 1; //Workaround to cancel incorrect edge on beginning.
8000644: 4b10 ldr r3, [pc, #64] ; (8000688 <main+0x108>)
8000646: 6adb ldr r3, [r3, #44] ; 0x2c
8000648: 4a0f ldr r2, [pc, #60] ; (8000688 <main+0x108>)
800064a: 3b01 subs r3, #1
800064c: 6253 str r3, [r2, #36] ; 0x24
TIM1->BDTR = TIM_BDTR_MOE; //Master Output Enable
800064e: 4b0e ldr r3, [pc, #56] ; (8000688 <main+0x108>)
8000650: f44f 4200 mov.w r2, #32768 ; 0x8000
8000654: 645a str r2, [r3, #68] ; 0x44
TIM1->CR1 = TIM_CR1_CEN; //Start timer (DMA transfer will begin)
8000656: 4b0c ldr r3, [pc, #48] ; (8000688 <main+0x108>)
8000658: 2201 movs r2, #1
800065a: 601a str r2, [r3, #0]
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
800065c: e7fe b.n 800065c <main+0xdc>
800065e: bf00 nop
8000660: 20000070 .word 0x20000070
8000664: 40020014 .word 0x40020014
8000668: 40020414 .word 0x40020414
800066c: 08002c14 .word 0x08002c14
8000670: 40023800 .word 0x40023800
8000674: 40020000 .word 0x40020000
8000678: 400264a0 .word 0x400264a0
800067c: 0c000451 .word 0x0c000451
8000680: 40026440 .word 0x40026440
8000684: 0c000441 .word 0x0c000441
8000688: 40010000 .word 0x40010000
0800068c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800068c: b580 push {r7, lr}
800068e: b094 sub sp, #80 ; 0x50
8000690: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000692: f107 0320 add.w r3, r7, #32
8000696: 2230 movs r2, #48 ; 0x30
8000698: 2100 movs r1, #0
800069a: 4618 mov r0, r3
800069c: f002 faa6 bl 8002bec <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80006a0: f107 030c add.w r3, r7, #12
80006a4: 2200 movs r2, #0
80006a6: 601a str r2, [r3, #0]
80006a8: 605a str r2, [r3, #4]
80006aa: 609a str r2, [r3, #8]
80006ac: 60da str r2, [r3, #12]
80006ae: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80006b0: 2300 movs r3, #0
80006b2: 60bb str r3, [r7, #8]
80006b4: 4b28 ldr r3, [pc, #160] ; (8000758 <SystemClock_Config+0xcc>)
80006b6: 6c1b ldr r3, [r3, #64] ; 0x40
80006b8: 4a27 ldr r2, [pc, #156] ; (8000758 <SystemClock_Config+0xcc>)
80006ba: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80006be: 6413 str r3, [r2, #64] ; 0x40
80006c0: 4b25 ldr r3, [pc, #148] ; (8000758 <SystemClock_Config+0xcc>)
80006c2: 6c1b ldr r3, [r3, #64] ; 0x40
80006c4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80006c8: 60bb str r3, [r7, #8]
80006ca: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
80006cc: 2300 movs r3, #0
80006ce: 607b str r3, [r7, #4]
80006d0: 4b22 ldr r3, [pc, #136] ; (800075c <SystemClock_Config+0xd0>)
80006d2: 681b ldr r3, [r3, #0]
80006d4: f423 4340 bic.w r3, r3, #49152 ; 0xc000
80006d8: 4a20 ldr r2, [pc, #128] ; (800075c <SystemClock_Config+0xd0>)
80006da: f443 4300 orr.w r3, r3, #32768 ; 0x8000
80006de: 6013 str r3, [r2, #0]
80006e0: 4b1e ldr r3, [pc, #120] ; (800075c <SystemClock_Config+0xd0>)
80006e2: 681b ldr r3, [r3, #0]
80006e4: f403 4340 and.w r3, r3, #49152 ; 0xc000
80006e8: 607b str r3, [r7, #4]
80006ea: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80006ec: 2302 movs r3, #2
80006ee: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80006f0: 2301 movs r3, #1
80006f2: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80006f4: 2310 movs r3, #16
80006f6: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80006f8: 2302 movs r3, #2
80006fa: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80006fc: 2300 movs r3, #0
80006fe: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 8;
8000700: 2308 movs r3, #8
8000702: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 84;
8000704: 2354 movs r3, #84 ; 0x54
8000706: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000708: 2302 movs r3, #2
800070a: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 4;
800070c: 2304 movs r3, #4
800070e: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000710: f107 0320 add.w r3, r7, #32
8000714: 4618 mov r0, r3
8000716: f000 fe2d bl 8001374 <HAL_RCC_OscConfig>
800071a: 4603 mov r3, r0
800071c: 2b00 cmp r3, #0
800071e: d001 beq.n 8000724 <SystemClock_Config+0x98>
{
Error_Handler();
8000720: f000 f9b8 bl 8000a94 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000724: 230f movs r3, #15
8000726: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000728: 2302 movs r3, #2
800072a: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800072c: 2300 movs r3, #0
800072e: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000730: f44f 5380 mov.w r3, #4096 ; 0x1000
8000734: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000736: 2300 movs r3, #0
8000738: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
800073a: f107 030c add.w r3, r7, #12
800073e: 2102 movs r1, #2
8000740: 4618 mov r0, r3
8000742: f001 f88f bl 8001864 <HAL_RCC_ClockConfig>
8000746: 4603 mov r3, r0
8000748: 2b00 cmp r3, #0
800074a: d001 beq.n 8000750 <SystemClock_Config+0xc4>
{
Error_Handler();
800074c: f000 f9a2 bl 8000a94 <Error_Handler>
}
}
8000750: bf00 nop
8000752: 3750 adds r7, #80 ; 0x50
8000754: 46bd mov sp, r7
8000756: bd80 pop {r7, pc}
8000758: 40023800 .word 0x40023800
800075c: 40007000 .word 0x40007000
08000760 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000760: b580 push {r7, lr}
8000762: b096 sub sp, #88 ; 0x58
8000764: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000766: f107 0348 add.w r3, r7, #72 ; 0x48
800076a: 2200 movs r2, #0
800076c: 601a str r2, [r3, #0]
800076e: 605a str r2, [r3, #4]
8000770: 609a str r2, [r3, #8]
8000772: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000774: f107 0340 add.w r3, r7, #64 ; 0x40
8000778: 2200 movs r2, #0
800077a: 601a str r2, [r3, #0]
800077c: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
800077e: f107 0324 add.w r3, r7, #36 ; 0x24
8000782: 2200 movs r2, #0
8000784: 601a str r2, [r3, #0]
8000786: 605a str r2, [r3, #4]
8000788: 609a str r2, [r3, #8]
800078a: 60da str r2, [r3, #12]
800078c: 611a str r2, [r3, #16]
800078e: 615a str r2, [r3, #20]
8000790: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8000792: 1d3b adds r3, r7, #4
8000794: 2220 movs r2, #32
8000796: 2100 movs r1, #0
8000798: 4618 mov r0, r3
800079a: f002 fa27 bl 8002bec <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
800079e: 4b58 ldr r3, [pc, #352] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007a0: 4a58 ldr r2, [pc, #352] ; (8000904 <MX_TIM1_Init+0x1a4>)
80007a2: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
80007a4: 4b56 ldr r3, [pc, #344] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007a6: 2200 movs r2, #0
80007a8: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80007aa: 4b55 ldr r3, [pc, #340] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007ac: 2200 movs r2, #0
80007ae: 609a str r2, [r3, #8]
htim1.Init.Period = 83;
80007b0: 4b53 ldr r3, [pc, #332] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007b2: 2253 movs r2, #83 ; 0x53
80007b4: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80007b6: 4b52 ldr r3, [pc, #328] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007b8: 2200 movs r2, #0
80007ba: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
80007bc: 4b50 ldr r3, [pc, #320] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007be: 2200 movs r2, #0
80007c0: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
80007c2: 4b4f ldr r3, [pc, #316] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007c4: 2280 movs r2, #128 ; 0x80
80007c6: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
80007c8: 484d ldr r0, [pc, #308] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007ca: f001 f9f7 bl 8001bbc <HAL_TIM_Base_Init>
80007ce: 4603 mov r3, r0
80007d0: 2b00 cmp r3, #0
80007d2: d001 beq.n 80007d8 <MX_TIM1_Init+0x78>
{
Error_Handler();
80007d4: f000 f95e bl 8000a94 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80007d8: f44f 5380 mov.w r3, #4096 ; 0x1000
80007dc: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
80007de: f107 0348 add.w r3, r7, #72 ; 0x48
80007e2: 4619 mov r1, r3
80007e4: 4846 ldr r0, [pc, #280] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007e6: f001 fd73 bl 80022d0 <HAL_TIM_ConfigClockSource>
80007ea: 4603 mov r3, r0
80007ec: 2b00 cmp r3, #0
80007ee: d001 beq.n 80007f4 <MX_TIM1_Init+0x94>
{
Error_Handler();
80007f0: f000 f950 bl 8000a94 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
80007f4: 4842 ldr r0, [pc, #264] ; (8000900 <MX_TIM1_Init+0x1a0>)
80007f6: f001 faec bl 8001dd2 <HAL_TIM_PWM_Init>
80007fa: 4603 mov r3, r0
80007fc: 2b00 cmp r3, #0
80007fe: d001 beq.n 8000804 <MX_TIM1_Init+0xa4>
{
Error_Handler();
8000800: f000 f948 bl 8000a94 <Error_Handler>
}
if (HAL_TIM_OC_Init(&htim1) != HAL_OK)
8000804: 483e ldr r0, [pc, #248] ; (8000900 <MX_TIM1_Init+0x1a0>)
8000806: f001 fa8b bl 8001d20 <HAL_TIM_OC_Init>
800080a: 4603 mov r3, r0
800080c: 2b00 cmp r3, #0
800080e: d001 beq.n 8000814 <MX_TIM1_Init+0xb4>
{
Error_Handler();
8000810: f000 f940 bl 8000a94 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000814: 2300 movs r3, #0
8000816: 643b str r3, [r7, #64] ; 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000818: 2300 movs r3, #0
800081a: 647b str r3, [r7, #68] ; 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
800081c: f107 0340 add.w r3, r7, #64 ; 0x40
8000820: 4619 mov r1, r3
8000822: 4837 ldr r0, [pc, #220] ; (8000900 <MX_TIM1_Init+0x1a0>)
8000824: f002 f8ea bl 80029fc <HAL_TIMEx_MasterConfigSynchronization>
8000828: 4603 mov r3, r0
800082a: 2b00 cmp r3, #0
800082c: d001 beq.n 8000832 <MX_TIM1_Init+0xd2>
{
Error_Handler();
800082e: f000 f931 bl 8000a94 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000832: 2360 movs r3, #96 ; 0x60
8000834: 627b str r3, [r7, #36] ; 0x24
sConfigOC.Pulse = 0;
8000836: 2300 movs r3, #0
8000838: 62bb str r3, [r7, #40] ; 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800083a: 2300 movs r3, #0
800083c: 62fb str r3, [r7, #44] ; 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
800083e: 2300 movs r3, #0
8000840: 633b str r3, [r7, #48] ; 0x30
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000842: 2300 movs r3, #0
8000844: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_SET;
8000846: f44f 7380 mov.w r3, #256 ; 0x100
800084a: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
800084c: 2300 movs r3, #0
800084e: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000850: f107 0324 add.w r3, r7, #36 ; 0x24
8000854: 2200 movs r2, #0
8000856: 4619 mov r1, r3
8000858: 4829 ldr r0, [pc, #164] ; (8000900 <MX_TIM1_Init+0x1a0>)
800085a: f001 fc77 bl 800214c <HAL_TIM_PWM_ConfigChannel>
800085e: 4603 mov r3, r0
8000860: 2b00 cmp r3, #0
8000862: d001 beq.n 8000868 <MX_TIM1_Init+0x108>
{
Error_Handler();
8000864: f000 f916 bl 8000a94 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_TIMING;
8000868: 2300 movs r3, #0
800086a: 627b str r3, [r7, #36] ; 0x24
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
800086c: 2300 movs r3, #0
800086e: 63bb str r3, [r7, #56] ; 0x38
if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000870: f107 0324 add.w r3, r7, #36 ; 0x24
8000874: 2204 movs r2, #4
8000876: 4619 mov r1, r3
8000878: 4821 ldr r0, [pc, #132] ; (8000900 <MX_TIM1_Init+0x1a0>)
800087a: f001 fc0b bl 8002094 <HAL_TIM_OC_ConfigChannel>
800087e: 4603 mov r3, r0
8000880: 2b00 cmp r3, #0
8000882: d001 beq.n 8000888 <MX_TIM1_Init+0x128>
{
Error_Handler();
8000884: f000 f906 bl 8000a94 <Error_Handler>
}
__HAL_TIM_ENABLE_OCxPRELOAD(&htim1, TIM_CHANNEL_2);
8000888: 4b1d ldr r3, [pc, #116] ; (8000900 <MX_TIM1_Init+0x1a0>)
800088a: 681b ldr r3, [r3, #0]
800088c: 699a ldr r2, [r3, #24]
800088e: 4b1c ldr r3, [pc, #112] ; (8000900 <MX_TIM1_Init+0x1a0>)
8000890: 681b ldr r3, [r3, #0]
8000892: f442 6200 orr.w r2, r2, #2048 ; 0x800
8000896: 619a str r2, [r3, #24]
if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000898: f107 0324 add.w r3, r7, #36 ; 0x24
800089c: 2208 movs r2, #8
800089e: 4619 mov r1, r3
80008a0: 4817 ldr r0, [pc, #92] ; (8000900 <MX_TIM1_Init+0x1a0>)
80008a2: f001 fbf7 bl 8002094 <HAL_TIM_OC_ConfigChannel>
80008a6: 4603 mov r3, r0
80008a8: 2b00 cmp r3, #0
80008aa: d001 beq.n 80008b0 <MX_TIM1_Init+0x150>
{
Error_Handler();
80008ac: f000 f8f2 bl 8000a94 <Error_Handler>
}
__HAL_TIM_ENABLE_OCxPRELOAD(&htim1, TIM_CHANNEL_3);
80008b0: 4b13 ldr r3, [pc, #76] ; (8000900 <MX_TIM1_Init+0x1a0>)
80008b2: 681b ldr r3, [r3, #0]
80008b4: 69da ldr r2, [r3, #28]
80008b6: 4b12 ldr r3, [pc, #72] ; (8000900 <MX_TIM1_Init+0x1a0>)
80008b8: 681b ldr r3, [r3, #0]
80008ba: f042 0208 orr.w r2, r2, #8
80008be: 61da str r2, [r3, #28]
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
80008c0: 2300 movs r3, #0
80008c2: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80008c4: 2300 movs r3, #0
80008c6: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80008c8: 2300 movs r3, #0
80008ca: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
80008cc: 2300 movs r3, #0
80008ce: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
80008d0: 2300 movs r3, #0
80008d2: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
80008d4: f44f 5300 mov.w r3, #8192 ; 0x2000
80008d8: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
80008da: 2300 movs r3, #0
80008dc: 623b str r3, [r7, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
80008de: 1d3b adds r3, r7, #4
80008e0: 4619 mov r1, r3
80008e2: 4807 ldr r0, [pc, #28] ; (8000900 <MX_TIM1_Init+0x1a0>)
80008e4: f002 f8f8 bl 8002ad8 <HAL_TIMEx_ConfigBreakDeadTime>
80008e8: 4603 mov r3, r0
80008ea: 2b00 cmp r3, #0
80008ec: d001 beq.n 80008f2 <MX_TIM1_Init+0x192>
{
Error_Handler();
80008ee: f000 f8d1 bl 8000a94 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
80008f2: 4803 ldr r0, [pc, #12] ; (8000900 <MX_TIM1_Init+0x1a0>)
80008f4: f000 f94a bl 8000b8c <HAL_TIM_MspPostInit>
}
80008f8: bf00 nop
80008fa: 3758 adds r7, #88 ; 0x58
80008fc: 46bd mov sp, r7
80008fe: bd80 pop {r7, pc}
8000900: 20000028 .word 0x20000028
8000904: 40010000 .word 0x40010000
08000908 <MX_TIM11_Init>:
* @brief TIM11 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM11_Init(void)
{
8000908: b580 push {r7, lr}
800090a: af00 add r7, sp, #0
/* USER CODE END TIM11_Init 0 */
/* USER CODE BEGIN TIM11_Init 1 */
/* USER CODE END TIM11_Init 1 */
htim11.Instance = TIM11;
800090c: 4b0e ldr r3, [pc, #56] ; (8000948 <MX_TIM11_Init+0x40>)
800090e: 4a0f ldr r2, [pc, #60] ; (800094c <MX_TIM11_Init+0x44>)
8000910: 601a str r2, [r3, #0]
htim11.Init.Prescaler = 839;
8000912: 4b0d ldr r3, [pc, #52] ; (8000948 <MX_TIM11_Init+0x40>)
8000914: f240 3247 movw r2, #839 ; 0x347
8000918: 605a str r2, [r3, #4]
htim11.Init.CounterMode = TIM_COUNTERMODE_UP;
800091a: 4b0b ldr r3, [pc, #44] ; (8000948 <MX_TIM11_Init+0x40>)
800091c: 2200 movs r2, #0
800091e: 609a str r2, [r3, #8]
htim11.Init.Period = 9999;
8000920: 4b09 ldr r3, [pc, #36] ; (8000948 <MX_TIM11_Init+0x40>)
8000922: f242 720f movw r2, #9999 ; 0x270f
8000926: 60da str r2, [r3, #12]
htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000928: 4b07 ldr r3, [pc, #28] ; (8000948 <MX_TIM11_Init+0x40>)
800092a: 2200 movs r2, #0
800092c: 611a str r2, [r3, #16]
htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
800092e: 4b06 ldr r3, [pc, #24] ; (8000948 <MX_TIM11_Init+0x40>)
8000930: 2280 movs r2, #128 ; 0x80
8000932: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim11) != HAL_OK)
8000934: 4804 ldr r0, [pc, #16] ; (8000948 <MX_TIM11_Init+0x40>)
8000936: f001 f941 bl 8001bbc <HAL_TIM_Base_Init>
800093a: 4603 mov r3, r0
800093c: 2b00 cmp r3, #0
800093e: d001 beq.n 8000944 <MX_TIM11_Init+0x3c>
{
Error_Handler();
8000940: f000 f8a8 bl 8000a94 <Error_Handler>
}
/* USER CODE BEGIN TIM11_Init 2 */
/* USER CODE END TIM11_Init 2 */
}
8000944: bf00 nop
8000946: bd80 pop {r7, pc}
8000948: 20000070 .word 0x20000070
800094c: 40014800 .word 0x40014800
08000950 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000950: b580 push {r7, lr}
8000952: b08a sub sp, #40 ; 0x28
8000954: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000956: f107 0314 add.w r3, r7, #20
800095a: 2200 movs r2, #0
800095c: 601a str r2, [r3, #0]
800095e: 605a str r2, [r3, #4]
8000960: 609a str r2, [r3, #8]
8000962: 60da str r2, [r3, #12]
8000964: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000966: 2300 movs r3, #0
8000968: 613b str r3, [r7, #16]
800096a: 4b3a ldr r3, [pc, #232] ; (8000a54 <MX_GPIO_Init+0x104>)
800096c: 6b1b ldr r3, [r3, #48] ; 0x30
800096e: 4a39 ldr r2, [pc, #228] ; (8000a54 <MX_GPIO_Init+0x104>)
8000970: f043 0304 orr.w r3, r3, #4
8000974: 6313 str r3, [r2, #48] ; 0x30
8000976: 4b37 ldr r3, [pc, #220] ; (8000a54 <MX_GPIO_Init+0x104>)
8000978: 6b1b ldr r3, [r3, #48] ; 0x30
800097a: f003 0304 and.w r3, r3, #4
800097e: 613b str r3, [r7, #16]
8000980: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000982: 2300 movs r3, #0
8000984: 60fb str r3, [r7, #12]
8000986: 4b33 ldr r3, [pc, #204] ; (8000a54 <MX_GPIO_Init+0x104>)
8000988: 6b1b ldr r3, [r3, #48] ; 0x30
800098a: 4a32 ldr r2, [pc, #200] ; (8000a54 <MX_GPIO_Init+0x104>)
800098c: f043 0380 orr.w r3, r3, #128 ; 0x80
8000990: 6313 str r3, [r2, #48] ; 0x30
8000992: 4b30 ldr r3, [pc, #192] ; (8000a54 <MX_GPIO_Init+0x104>)
8000994: 6b1b ldr r3, [r3, #48] ; 0x30
8000996: f003 0380 and.w r3, r3, #128 ; 0x80
800099a: 60fb str r3, [r7, #12]
800099c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800099e: 2300 movs r3, #0
80009a0: 60bb str r3, [r7, #8]
80009a2: 4b2c ldr r3, [pc, #176] ; (8000a54 <MX_GPIO_Init+0x104>)
80009a4: 6b1b ldr r3, [r3, #48] ; 0x30
80009a6: 4a2b ldr r2, [pc, #172] ; (8000a54 <MX_GPIO_Init+0x104>)
80009a8: f043 0301 orr.w r3, r3, #1
80009ac: 6313 str r3, [r2, #48] ; 0x30
80009ae: 4b29 ldr r3, [pc, #164] ; (8000a54 <MX_GPIO_Init+0x104>)
80009b0: 6b1b ldr r3, [r3, #48] ; 0x30
80009b2: f003 0301 and.w r3, r3, #1
80009b6: 60bb str r3, [r7, #8]
80009b8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80009ba: 2300 movs r3, #0
80009bc: 607b str r3, [r7, #4]
80009be: 4b25 ldr r3, [pc, #148] ; (8000a54 <MX_GPIO_Init+0x104>)
80009c0: 6b1b ldr r3, [r3, #48] ; 0x30
80009c2: 4a24 ldr r2, [pc, #144] ; (8000a54 <MX_GPIO_Init+0x104>)
80009c4: f043 0302 orr.w r3, r3, #2
80009c8: 6313 str r3, [r2, #48] ; 0x30
80009ca: 4b22 ldr r3, [pc, #136] ; (8000a54 <MX_GPIO_Init+0x104>)
80009cc: 6b1b ldr r3, [r3, #48] ; 0x30
80009ce: f003 0302 and.w r3, r3, #2
80009d2: 607b str r3, [r7, #4]
80009d4: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
80009d6: 2200 movs r2, #0
80009d8: f44f 5100 mov.w r1, #8192 ; 0x2000
80009dc: 481e ldr r0, [pc, #120] ; (8000a58 <MX_GPIO_Init+0x108>)
80009de: f000 fc95 bl 800130c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
80009e2: 2200 movs r2, #0
80009e4: 21ff movs r1, #255 ; 0xff
80009e6: 481d ldr r0, [pc, #116] ; (8000a5c <MX_GPIO_Init+0x10c>)
80009e8: f000 fc90 bl 800130c <HAL_GPIO_WritePin>
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
80009ec: 2200 movs r2, #0
80009ee: 21ff movs r1, #255 ; 0xff
80009f0: 481b ldr r0, [pc, #108] ; (8000a60 <MX_GPIO_Init+0x110>)
80009f2: f000 fc8b bl 800130c <HAL_GPIO_WritePin>
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
/*Configure GPIO pin : PC13 */
GPIO_InitStruct.Pin = GPIO_PIN_13;
80009f6: f44f 5300 mov.w r3, #8192 ; 0x2000
80009fa: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80009fc: 2301 movs r3, #1
80009fe: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a00: 2300 movs r3, #0
8000a02: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a04: 2300 movs r3, #0
8000a06: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000a08: f107 0314 add.w r3, r7, #20
8000a0c: 4619 mov r1, r3
8000a0e: 4812 ldr r0, [pc, #72] ; (8000a58 <MX_GPIO_Init+0x108>)
8000a10: f000 faf8 bl 8001004 <HAL_GPIO_Init>
/*Configure GPIO pins : PA0 PA1 PA2 PA3
PA4 PA5 PA6 PA7 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
8000a14: 23ff movs r3, #255 ; 0xff
8000a16: 617b str r3, [r7, #20]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a18: 2301 movs r3, #1
8000a1a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a1c: 2300 movs r3, #0
8000a1e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a20: 2303 movs r3, #3
8000a22: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a24: f107 0314 add.w r3, r7, #20
8000a28: 4619 mov r1, r3
8000a2a: 480c ldr r0, [pc, #48] ; (8000a5c <MX_GPIO_Init+0x10c>)
8000a2c: f000 faea bl 8001004 <HAL_GPIO_Init>
/*Configure GPIO pins : PB0 PB1 PB2 PB3
PB4 PB5 PB6 PB7 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
8000a30: 23ff movs r3, #255 ; 0xff
8000a32: 617b str r3, [r7, #20]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a34: 2301 movs r3, #1
8000a36: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a38: 2300 movs r3, #0
8000a3a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a3c: 2303 movs r3, #3
8000a3e: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a40: f107 0314 add.w r3, r7, #20
8000a44: 4619 mov r1, r3
8000a46: 4806 ldr r0, [pc, #24] ; (8000a60 <MX_GPIO_Init+0x110>)
8000a48: f000 fadc bl 8001004 <HAL_GPIO_Init>
}
8000a4c: bf00 nop
8000a4e: 3728 adds r7, #40 ; 0x28
8000a50: 46bd mov sp, r7
8000a52: bd80 pop {r7, pc}
8000a54: 40023800 .word 0x40023800
8000a58: 40020800 .word 0x40020800
8000a5c: 40020000 .word 0x40020000
8000a60: 40020400 .word 0x40020400
08000a64 <HAL_TIM_PeriodElapsedCallback>:
/* USER CODE BEGIN 4 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim){
8000a64: b580 push {r7, lr}
8000a66: b082 sub sp, #8
8000a68: af00 add r7, sp, #0
8000a6a: 6078 str r0, [r7, #4]
if(htim->Instance == htim11.Instance)
8000a6c: 687b ldr r3, [r7, #4]
8000a6e: 681a ldr r2, [r3, #0]
8000a70: 4b06 ldr r3, [pc, #24] ; (8000a8c <HAL_TIM_PeriodElapsedCallback+0x28>)
8000a72: 681b ldr r3, [r3, #0]
8000a74: 429a cmp r2, r3
8000a76: d104 bne.n 8000a82 <HAL_TIM_PeriodElapsedCallback+0x1e>
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
8000a78: f44f 5100 mov.w r1, #8192 ; 0x2000
8000a7c: 4804 ldr r0, [pc, #16] ; (8000a90 <HAL_TIM_PeriodElapsedCallback+0x2c>)
8000a7e: f000 fc5e bl 800133e <HAL_GPIO_TogglePin>
}
8000a82: bf00 nop
8000a84: 3708 adds r7, #8
8000a86: 46bd mov sp, r7
8000a88: bd80 pop {r7, pc}
8000a8a: bf00 nop
8000a8c: 20000070 .word 0x20000070
8000a90: 40020800 .word 0x40020800
08000a94 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000a94: b480 push {r7}
8000a96: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000a98: b672 cpsid i
}
8000a9a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000a9c: e7fe b.n 8000a9c <Error_Handler+0x8>
...
08000aa0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000aa0: b480 push {r7}
8000aa2: b083 sub sp, #12
8000aa4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000aa6: 2300 movs r3, #0
8000aa8: 607b str r3, [r7, #4]
8000aaa: 4b10 ldr r3, [pc, #64] ; (8000aec <HAL_MspInit+0x4c>)
8000aac: 6c5b ldr r3, [r3, #68] ; 0x44
8000aae: 4a0f ldr r2, [pc, #60] ; (8000aec <HAL_MspInit+0x4c>)
8000ab0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000ab4: 6453 str r3, [r2, #68] ; 0x44
8000ab6: 4b0d ldr r3, [pc, #52] ; (8000aec <HAL_MspInit+0x4c>)
8000ab8: 6c5b ldr r3, [r3, #68] ; 0x44
8000aba: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000abe: 607b str r3, [r7, #4]
8000ac0: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000ac2: 2300 movs r3, #0
8000ac4: 603b str r3, [r7, #0]
8000ac6: 4b09 ldr r3, [pc, #36] ; (8000aec <HAL_MspInit+0x4c>)
8000ac8: 6c1b ldr r3, [r3, #64] ; 0x40
8000aca: 4a08 ldr r2, [pc, #32] ; (8000aec <HAL_MspInit+0x4c>)
8000acc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000ad0: 6413 str r3, [r2, #64] ; 0x40
8000ad2: 4b06 ldr r3, [pc, #24] ; (8000aec <HAL_MspInit+0x4c>)
8000ad4: 6c1b ldr r3, [r3, #64] ; 0x40
8000ad6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000ada: 603b str r3, [r7, #0]
8000adc: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000ade: bf00 nop
8000ae0: 370c adds r7, #12
8000ae2: 46bd mov sp, r7
8000ae4: f85d 7b04 ldr.w r7, [sp], #4
8000ae8: 4770 bx lr
8000aea: bf00 nop
8000aec: 40023800 .word 0x40023800
08000af0 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000af0: b580 push {r7, lr}
8000af2: b084 sub sp, #16
8000af4: af00 add r7, sp, #0
8000af6: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000af8: 687b ldr r3, [r7, #4]
8000afa: 681b ldr r3, [r3, #0]
8000afc: 4a20 ldr r2, [pc, #128] ; (8000b80 <HAL_TIM_Base_MspInit+0x90>)
8000afe: 4293 cmp r3, r2
8000b00: d11e bne.n 8000b40 <HAL_TIM_Base_MspInit+0x50>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000b02: 2300 movs r3, #0
8000b04: 60fb str r3, [r7, #12]
8000b06: 4b1f ldr r3, [pc, #124] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b08: 6c5b ldr r3, [r3, #68] ; 0x44
8000b0a: 4a1e ldr r2, [pc, #120] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b0c: f043 0301 orr.w r3, r3, #1
8000b10: 6453 str r3, [r2, #68] ; 0x44
8000b12: 4b1c ldr r3, [pc, #112] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b14: 6c5b ldr r3, [r3, #68] ; 0x44
8000b16: f003 0301 and.w r3, r3, #1
8000b1a: 60fb str r3, [r7, #12]
8000b1c: 68fb ldr r3, [r7, #12]
/* TIM1 interrupt Init */
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
8000b1e: 2200 movs r2, #0
8000b20: 2100 movs r1, #0
8000b22: 2019 movs r0, #25
8000b24: f000 fa37 bl 8000f96 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
8000b28: 2019 movs r0, #25
8000b2a: f000 fa50 bl 8000fce <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 0, 0);
8000b2e: 2200 movs r2, #0
8000b30: 2100 movs r1, #0
8000b32: 201a movs r0, #26
8000b34: f000 fa2f bl 8000f96 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn);
8000b38: 201a movs r0, #26
8000b3a: f000 fa48 bl 8000fce <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM11_MspInit 1 */
/* USER CODE END TIM11_MspInit 1 */
}
}
8000b3e: e01a b.n 8000b76 <HAL_TIM_Base_MspInit+0x86>
else if(htim_base->Instance==TIM11)
8000b40: 687b ldr r3, [r7, #4]
8000b42: 681b ldr r3, [r3, #0]
8000b44: 4a10 ldr r2, [pc, #64] ; (8000b88 <HAL_TIM_Base_MspInit+0x98>)
8000b46: 4293 cmp r3, r2
8000b48: d115 bne.n 8000b76 <HAL_TIM_Base_MspInit+0x86>
__HAL_RCC_TIM11_CLK_ENABLE();
8000b4a: 2300 movs r3, #0
8000b4c: 60bb str r3, [r7, #8]
8000b4e: 4b0d ldr r3, [pc, #52] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b50: 6c5b ldr r3, [r3, #68] ; 0x44
8000b52: 4a0c ldr r2, [pc, #48] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b54: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000b58: 6453 str r3, [r2, #68] ; 0x44
8000b5a: 4b0a ldr r3, [pc, #40] ; (8000b84 <HAL_TIM_Base_MspInit+0x94>)
8000b5c: 6c5b ldr r3, [r3, #68] ; 0x44
8000b5e: f403 2380 and.w r3, r3, #262144 ; 0x40000
8000b62: 60bb str r3, [r7, #8]
8000b64: 68bb ldr r3, [r7, #8]
HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 0, 0);
8000b66: 2200 movs r2, #0
8000b68: 2100 movs r1, #0
8000b6a: 201a movs r0, #26
8000b6c: f000 fa13 bl 8000f96 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn);
8000b70: 201a movs r0, #26
8000b72: f000 fa2c bl 8000fce <HAL_NVIC_EnableIRQ>
}
8000b76: bf00 nop
8000b78: 3710 adds r7, #16
8000b7a: 46bd mov sp, r7
8000b7c: bd80 pop {r7, pc}
8000b7e: bf00 nop
8000b80: 40010000 .word 0x40010000
8000b84: 40023800 .word 0x40023800
8000b88: 40014800 .word 0x40014800
08000b8c <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000b8c: b580 push {r7, lr}
8000b8e: b088 sub sp, #32
8000b90: af00 add r7, sp, #0
8000b92: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000b94: f107 030c add.w r3, r7, #12
8000b98: 2200 movs r2, #0
8000b9a: 601a str r2, [r3, #0]
8000b9c: 605a str r2, [r3, #4]
8000b9e: 609a str r2, [r3, #8]
8000ba0: 60da str r2, [r3, #12]
8000ba2: 611a str r2, [r3, #16]
if(htim->Instance==TIM1)
8000ba4: 687b ldr r3, [r7, #4]
8000ba6: 681b ldr r3, [r3, #0]
8000ba8: 4a12 ldr r2, [pc, #72] ; (8000bf4 <HAL_TIM_MspPostInit+0x68>)
8000baa: 4293 cmp r3, r2
8000bac: d11e bne.n 8000bec <HAL_TIM_MspPostInit+0x60>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000bae: 2300 movs r3, #0
8000bb0: 60bb str r3, [r7, #8]
8000bb2: 4b11 ldr r3, [pc, #68] ; (8000bf8 <HAL_TIM_MspPostInit+0x6c>)
8000bb4: 6b1b ldr r3, [r3, #48] ; 0x30
8000bb6: 4a10 ldr r2, [pc, #64] ; (8000bf8 <HAL_TIM_MspPostInit+0x6c>)
8000bb8: f043 0301 orr.w r3, r3, #1
8000bbc: 6313 str r3, [r2, #48] ; 0x30
8000bbe: 4b0e ldr r3, [pc, #56] ; (8000bf8 <HAL_TIM_MspPostInit+0x6c>)
8000bc0: 6b1b ldr r3, [r3, #48] ; 0x30
8000bc2: f003 0301 and.w r3, r3, #1
8000bc6: 60bb str r3, [r7, #8]
8000bc8: 68bb ldr r3, [r7, #8]
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_8;
8000bca: f44f 7380 mov.w r3, #256 ; 0x100
8000bce: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bd0: 2302 movs r3, #2
8000bd2: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000bd4: 2301 movs r3, #1
8000bd6: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000bd8: 2303 movs r3, #3
8000bda: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
8000bdc: 2301 movs r3, #1
8000bde: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000be0: f107 030c add.w r3, r7, #12
8000be4: 4619 mov r1, r3
8000be6: 4805 ldr r0, [pc, #20] ; (8000bfc <HAL_TIM_MspPostInit+0x70>)
8000be8: f000 fa0c bl 8001004 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
8000bec: bf00 nop
8000bee: 3720 adds r7, #32
8000bf0: 46bd mov sp, r7
8000bf2: bd80 pop {r7, pc}
8000bf4: 40010000 .word 0x40010000
8000bf8: 40023800 .word 0x40023800
8000bfc: 40020000 .word 0x40020000
08000c00 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000c00: b480 push {r7}
8000c02: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000c04: e7fe b.n 8000c04 <NMI_Handler+0x4>
08000c06 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000c06: b480 push {r7}
8000c08: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000c0a: e7fe b.n 8000c0a <HardFault_Handler+0x4>
08000c0c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000c0c: b480 push {r7}
8000c0e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000c10: e7fe b.n 8000c10 <MemManage_Handler+0x4>
08000c12 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000c12: b480 push {r7}
8000c14: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000c16: e7fe b.n 8000c16 <BusFault_Handler+0x4>
08000c18 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000c18: b480 push {r7}
8000c1a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000c1c: e7fe b.n 8000c1c <UsageFault_Handler+0x4>
08000c1e <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000c1e: b480 push {r7}
8000c20: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000c22: bf00 nop
8000c24: 46bd mov sp, r7
8000c26: f85d 7b04 ldr.w r7, [sp], #4
8000c2a: 4770 bx lr
08000c2c <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000c2c: b480 push {r7}
8000c2e: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000c30: bf00 nop
8000c32: 46bd mov sp, r7
8000c34: f85d 7b04 ldr.w r7, [sp], #4
8000c38: 4770 bx lr
08000c3a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000c3a: b480 push {r7}
8000c3c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000c3e: bf00 nop
8000c40: 46bd mov sp, r7
8000c42: f85d 7b04 ldr.w r7, [sp], #4
8000c46: 4770 bx lr
08000c48 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000c48: b580 push {r7, lr}
8000c4a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000c4c: f000 f8a8 bl 8000da0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000c50: bf00 nop
8000c52: bd80 pop {r7, pc}
08000c54 <TIM1_UP_TIM10_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
*/
void TIM1_UP_TIM10_IRQHandler(void)
{
8000c54: b580 push {r7, lr}
8000c56: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
/* USER CODE END TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000c58: 4802 ldr r0, [pc, #8] ; (8000c64 <TIM1_UP_TIM10_IRQHandler+0x10>)
8000c5a: f001 f913 bl 8001e84 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
/* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
8000c5e: bf00 nop
8000c60: bd80 pop {r7, pc}
8000c62: bf00 nop
8000c64: 20000028 .word 0x20000028
08000c68 <TIM1_TRG_COM_TIM11_IRQHandler>:
/**
* @brief This function handles TIM1 trigger and commutation interrupts and TIM11 global interrupt.
*/
void TIM1_TRG_COM_TIM11_IRQHandler(void)
{
8000c68: b580 push {r7, lr}
8000c6a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 0 */
/* USER CODE END TIM1_TRG_COM_TIM11_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000c6c: 4803 ldr r0, [pc, #12] ; (8000c7c <TIM1_TRG_COM_TIM11_IRQHandler+0x14>)
8000c6e: f001 f909 bl 8001e84 <HAL_TIM_IRQHandler>
HAL_TIM_IRQHandler(&htim11);
8000c72: 4803 ldr r0, [pc, #12] ; (8000c80 <TIM1_TRG_COM_TIM11_IRQHandler+0x18>)
8000c74: f001 f906 bl 8001e84 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 1 */
/* USER CODE END TIM1_TRG_COM_TIM11_IRQn 1 */
}
8000c78: bf00 nop
8000c7a: bd80 pop {r7, pc}
8000c7c: 20000028 .word 0x20000028
8000c80: 20000070 .word 0x20000070
08000c84 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000c84: b480 push {r7}
8000c86: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000c88: 4b06 ldr r3, [pc, #24] ; (8000ca4 <SystemInit+0x20>)
8000c8a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000c8e: 4a05 ldr r2, [pc, #20] ; (8000ca4 <SystemInit+0x20>)
8000c90: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000c94: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000c98: bf00 nop
8000c9a: 46bd mov sp, r7
8000c9c: f85d 7b04 ldr.w r7, [sp], #4
8000ca0: 4770 bx lr
8000ca2: bf00 nop
8000ca4: e000ed00 .word 0xe000ed00
08000ca8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000ca8: f8df d034 ldr.w sp, [pc, #52] ; 8000ce0 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000cac: 480d ldr r0, [pc, #52] ; (8000ce4 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000cae: 490e ldr r1, [pc, #56] ; (8000ce8 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000cb0: 4a0e ldr r2, [pc, #56] ; (8000cec <LoopFillZerobss+0x1e>)
movs r3, #0
8000cb2: 2300 movs r3, #0
b LoopCopyDataInit
8000cb4: e002 b.n 8000cbc <LoopCopyDataInit>
08000cb6 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000cb6: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000cb8: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000cba: 3304 adds r3, #4
08000cbc <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000cbc: 18c4 adds r4, r0, r3
cmp r4, r1
8000cbe: 428c cmp r4, r1
bcc CopyDataInit
8000cc0: d3f9 bcc.n 8000cb6 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000cc2: 4a0b ldr r2, [pc, #44] ; (8000cf0 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000cc4: 4c0b ldr r4, [pc, #44] ; (8000cf4 <LoopFillZerobss+0x26>)
movs r3, #0
8000cc6: 2300 movs r3, #0
b LoopFillZerobss
8000cc8: e001 b.n 8000cce <LoopFillZerobss>
08000cca <FillZerobss>:
FillZerobss:
str r3, [r2]
8000cca: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000ccc: 3204 adds r2, #4
08000cce <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000cce: 42a2 cmp r2, r4
bcc FillZerobss
8000cd0: d3fb bcc.n 8000cca <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8000cd2: f7ff ffd7 bl 8000c84 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000cd6: f001 ff65 bl 8002ba4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000cda: f7ff fc51 bl 8000580 <main>
bx lr
8000cde: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000ce0: 20010000 .word 0x20010000
ldr r0, =_sdata
8000ce4: 20000000 .word 0x20000000
ldr r1, =_edata
8000ce8: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000cec: 08002c4c .word 0x08002c4c
ldr r2, =_sbss
8000cf0: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000cf4: 200000bc .word 0x200000bc
08000cf8 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000cf8: e7fe b.n 8000cf8 <ADC_IRQHandler>
...
08000cfc <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000cfc: b580 push {r7, lr}
8000cfe: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000d00: 4b0e ldr r3, [pc, #56] ; (8000d3c <HAL_Init+0x40>)
8000d02: 681b ldr r3, [r3, #0]
8000d04: 4a0d ldr r2, [pc, #52] ; (8000d3c <HAL_Init+0x40>)
8000d06: f443 7300 orr.w r3, r3, #512 ; 0x200
8000d0a: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000d0c: 4b0b ldr r3, [pc, #44] ; (8000d3c <HAL_Init+0x40>)
8000d0e: 681b ldr r3, [r3, #0]
8000d10: 4a0a ldr r2, [pc, #40] ; (8000d3c <HAL_Init+0x40>)
8000d12: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000d16: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000d18: 4b08 ldr r3, [pc, #32] ; (8000d3c <HAL_Init+0x40>)
8000d1a: 681b ldr r3, [r3, #0]
8000d1c: 4a07 ldr r2, [pc, #28] ; (8000d3c <HAL_Init+0x40>)
8000d1e: f443 7380 orr.w r3, r3, #256 ; 0x100
8000d22: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000d24: 2003 movs r0, #3
8000d26: f000 f92b bl 8000f80 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000d2a: 200f movs r0, #15
8000d2c: f000 f808 bl 8000d40 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000d30: f7ff feb6 bl 8000aa0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000d34: 2300 movs r3, #0
}
8000d36: 4618 mov r0, r3
8000d38: bd80 pop {r7, pc}
8000d3a: bf00 nop
8000d3c: 40023c00 .word 0x40023c00
08000d40 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000d40: b580 push {r7, lr}
8000d42: b082 sub sp, #8
8000d44: af00 add r7, sp, #0
8000d46: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000d48: 4b12 ldr r3, [pc, #72] ; (8000d94 <HAL_InitTick+0x54>)
8000d4a: 681a ldr r2, [r3, #0]
8000d4c: 4b12 ldr r3, [pc, #72] ; (8000d98 <HAL_InitTick+0x58>)
8000d4e: 781b ldrb r3, [r3, #0]
8000d50: 4619 mov r1, r3
8000d52: f44f 737a mov.w r3, #1000 ; 0x3e8
8000d56: fbb3 f3f1 udiv r3, r3, r1
8000d5a: fbb2 f3f3 udiv r3, r2, r3
8000d5e: 4618 mov r0, r3
8000d60: f000 f943 bl 8000fea <HAL_SYSTICK_Config>
8000d64: 4603 mov r3, r0
8000d66: 2b00 cmp r3, #0
8000d68: d001 beq.n 8000d6e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000d6a: 2301 movs r3, #1
8000d6c: e00e b.n 8000d8c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000d6e: 687b ldr r3, [r7, #4]
8000d70: 2b0f cmp r3, #15
8000d72: d80a bhi.n 8000d8a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000d74: 2200 movs r2, #0
8000d76: 6879 ldr r1, [r7, #4]
8000d78: f04f 30ff mov.w r0, #4294967295
8000d7c: f000 f90b bl 8000f96 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000d80: 4a06 ldr r2, [pc, #24] ; (8000d9c <HAL_InitTick+0x5c>)
8000d82: 687b ldr r3, [r7, #4]
8000d84: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000d86: 2300 movs r3, #0
8000d88: e000 b.n 8000d8c <HAL_InitTick+0x4c>
return HAL_ERROR;
8000d8a: 2301 movs r3, #1
}
8000d8c: 4618 mov r0, r3
8000d8e: 3708 adds r7, #8
8000d90: 46bd mov sp, r7
8000d92: bd80 pop {r7, pc}
8000d94: 20000000 .word 0x20000000
8000d98: 20000008 .word 0x20000008
8000d9c: 20000004 .word 0x20000004
08000da0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000da0: b480 push {r7}
8000da2: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000da4: 4b06 ldr r3, [pc, #24] ; (8000dc0 <HAL_IncTick+0x20>)
8000da6: 781b ldrb r3, [r3, #0]
8000da8: 461a mov r2, r3
8000daa: 4b06 ldr r3, [pc, #24] ; (8000dc4 <HAL_IncTick+0x24>)
8000dac: 681b ldr r3, [r3, #0]
8000dae: 4413 add r3, r2
8000db0: 4a04 ldr r2, [pc, #16] ; (8000dc4 <HAL_IncTick+0x24>)
8000db2: 6013 str r3, [r2, #0]
}
8000db4: bf00 nop
8000db6: 46bd mov sp, r7
8000db8: f85d 7b04 ldr.w r7, [sp], #4
8000dbc: 4770 bx lr
8000dbe: bf00 nop
8000dc0: 20000008 .word 0x20000008
8000dc4: 200000b8 .word 0x200000b8
08000dc8 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000dc8: b480 push {r7}
8000dca: af00 add r7, sp, #0
return uwTick;
8000dcc: 4b03 ldr r3, [pc, #12] ; (8000ddc <HAL_GetTick+0x14>)
8000dce: 681b ldr r3, [r3, #0]
}
8000dd0: 4618 mov r0, r3
8000dd2: 46bd mov sp, r7
8000dd4: f85d 7b04 ldr.w r7, [sp], #4
8000dd8: 4770 bx lr
8000dda: bf00 nop
8000ddc: 200000b8 .word 0x200000b8
08000de0 <__NVIC_SetPriorityGrouping>:
{
8000de0: b480 push {r7}
8000de2: b085 sub sp, #20
8000de4: af00 add r7, sp, #0
8000de6: 6078 str r0, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000de8: 687b ldr r3, [r7, #4]
8000dea: f003 0307 and.w r3, r3, #7
8000dee: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000df0: 4b0c ldr r3, [pc, #48] ; (8000e24 <__NVIC_SetPriorityGrouping+0x44>)
8000df2: 68db ldr r3, [r3, #12]
8000df4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000df6: 68ba ldr r2, [r7, #8]
8000df8: f64f 03ff movw r3, #63743 ; 0xf8ff
8000dfc: 4013 ands r3, r2
8000dfe: 60bb str r3, [r7, #8]
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000e00: 68fb ldr r3, [r7, #12]
8000e02: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000e04: 68bb ldr r3, [r7, #8]
8000e06: 4313 orrs r3, r2
reg_value = (reg_value |
8000e08: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000e0c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000e10: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000e12: 4a04 ldr r2, [pc, #16] ; (8000e24 <__NVIC_SetPriorityGrouping+0x44>)
8000e14: 68bb ldr r3, [r7, #8]
8000e16: 60d3 str r3, [r2, #12]
}
8000e18: bf00 nop
8000e1a: 3714 adds r7, #20
8000e1c: 46bd mov sp, r7
8000e1e: f85d 7b04 ldr.w r7, [sp], #4
8000e22: 4770 bx lr
8000e24: e000ed00 .word 0xe000ed00
08000e28 <__NVIC_GetPriorityGrouping>:
{
8000e28: b480 push {r7}
8000e2a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000e2c: 4b04 ldr r3, [pc, #16] ; (8000e40 <__NVIC_GetPriorityGrouping+0x18>)
8000e2e: 68db ldr r3, [r3, #12]
8000e30: 0a1b lsrs r3, r3, #8
8000e32: f003 0307 and.w r3, r3, #7
}
8000e36: 4618 mov r0, r3
8000e38: 46bd mov sp, r7
8000e3a: f85d 7b04 ldr.w r7, [sp], #4
8000e3e: 4770 bx lr
8000e40: e000ed00 .word 0xe000ed00
08000e44 <__NVIC_EnableIRQ>:
{
8000e44: b480 push {r7}
8000e46: b083 sub sp, #12
8000e48: af00 add r7, sp, #0
8000e4a: 4603 mov r3, r0
8000e4c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000e4e: f997 3007 ldrsb.w r3, [r7, #7]
8000e52: 2b00 cmp r3, #0
8000e54: db0b blt.n 8000e6e <__NVIC_EnableIRQ+0x2a>
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000e56: 79fb ldrb r3, [r7, #7]
8000e58: f003 021f and.w r2, r3, #31
8000e5c: 4907 ldr r1, [pc, #28] ; (8000e7c <__NVIC_EnableIRQ+0x38>)
8000e5e: f997 3007 ldrsb.w r3, [r7, #7]
8000e62: 095b lsrs r3, r3, #5
8000e64: 2001 movs r0, #1
8000e66: fa00 f202 lsl.w r2, r0, r2
8000e6a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
8000e6e: bf00 nop
8000e70: 370c adds r7, #12
8000e72: 46bd mov sp, r7
8000e74: f85d 7b04 ldr.w r7, [sp], #4
8000e78: 4770 bx lr
8000e7a: bf00 nop
8000e7c: e000e100 .word 0xe000e100
08000e80 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000e80: b480 push {r7}
8000e82: b083 sub sp, #12
8000e84: af00 add r7, sp, #0
8000e86: 4603 mov r3, r0
8000e88: 6039 str r1, [r7, #0]
8000e8a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000e8c: f997 3007 ldrsb.w r3, [r7, #7]
8000e90: 2b00 cmp r3, #0
8000e92: db0a blt.n 8000eaa <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000e94: 683b ldr r3, [r7, #0]
8000e96: b2da uxtb r2, r3
8000e98: 490c ldr r1, [pc, #48] ; (8000ecc <__NVIC_SetPriority+0x4c>)
8000e9a: f997 3007 ldrsb.w r3, [r7, #7]
8000e9e: 0112 lsls r2, r2, #4
8000ea0: b2d2 uxtb r2, r2
8000ea2: 440b add r3, r1
8000ea4: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000ea8: e00a b.n 8000ec0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000eaa: 683b ldr r3, [r7, #0]
8000eac: b2da uxtb r2, r3
8000eae: 4908 ldr r1, [pc, #32] ; (8000ed0 <__NVIC_SetPriority+0x50>)
8000eb0: 79fb ldrb r3, [r7, #7]
8000eb2: f003 030f and.w r3, r3, #15
8000eb6: 3b04 subs r3, #4
8000eb8: 0112 lsls r2, r2, #4
8000eba: b2d2 uxtb r2, r2
8000ebc: 440b add r3, r1
8000ebe: 761a strb r2, [r3, #24]
}
8000ec0: bf00 nop
8000ec2: 370c adds r7, #12
8000ec4: 46bd mov sp, r7
8000ec6: f85d 7b04 ldr.w r7, [sp], #4
8000eca: 4770 bx lr
8000ecc: e000e100 .word 0xe000e100
8000ed0: e000ed00 .word 0xe000ed00
08000ed4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ed4: b480 push {r7}
8000ed6: b089 sub sp, #36 ; 0x24
8000ed8: af00 add r7, sp, #0
8000eda: 60f8 str r0, [r7, #12]
8000edc: 60b9 str r1, [r7, #8]
8000ede: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000ee0: 68fb ldr r3, [r7, #12]
8000ee2: f003 0307 and.w r3, r3, #7
8000ee6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000ee8: 69fb ldr r3, [r7, #28]
8000eea: f1c3 0307 rsb r3, r3, #7
8000eee: 2b04 cmp r3, #4
8000ef0: bf28 it cs
8000ef2: 2304 movcs r3, #4
8000ef4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000ef6: 69fb ldr r3, [r7, #28]
8000ef8: 3304 adds r3, #4
8000efa: 2b06 cmp r3, #6
8000efc: d902 bls.n 8000f04 <NVIC_EncodePriority+0x30>
8000efe: 69fb ldr r3, [r7, #28]
8000f00: 3b03 subs r3, #3
8000f02: e000 b.n 8000f06 <NVIC_EncodePriority+0x32>
8000f04: 2300 movs r3, #0
8000f06: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000f08: f04f 32ff mov.w r2, #4294967295
8000f0c: 69bb ldr r3, [r7, #24]
8000f0e: fa02 f303 lsl.w r3, r2, r3
8000f12: 43da mvns r2, r3
8000f14: 68bb ldr r3, [r7, #8]
8000f16: 401a ands r2, r3
8000f18: 697b ldr r3, [r7, #20]
8000f1a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000f1c: f04f 31ff mov.w r1, #4294967295
8000f20: 697b ldr r3, [r7, #20]
8000f22: fa01 f303 lsl.w r3, r1, r3
8000f26: 43d9 mvns r1, r3
8000f28: 687b ldr r3, [r7, #4]
8000f2a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000f2c: 4313 orrs r3, r2
);
}
8000f2e: 4618 mov r0, r3
8000f30: 3724 adds r7, #36 ; 0x24
8000f32: 46bd mov sp, r7
8000f34: f85d 7b04 ldr.w r7, [sp], #4
8000f38: 4770 bx lr
...
08000f3c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000f3c: b580 push {r7, lr}
8000f3e: b082 sub sp, #8
8000f40: af00 add r7, sp, #0
8000f42: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000f44: 687b ldr r3, [r7, #4]
8000f46: 3b01 subs r3, #1
8000f48: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000f4c: d301 bcc.n 8000f52 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000f4e: 2301 movs r3, #1
8000f50: e00f b.n 8000f72 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000f52: 4a0a ldr r2, [pc, #40] ; (8000f7c <SysTick_Config+0x40>)
8000f54: 687b ldr r3, [r7, #4]
8000f56: 3b01 subs r3, #1
8000f58: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000f5a: 210f movs r1, #15
8000f5c: f04f 30ff mov.w r0, #4294967295
8000f60: f7ff ff8e bl 8000e80 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000f64: 4b05 ldr r3, [pc, #20] ; (8000f7c <SysTick_Config+0x40>)
8000f66: 2200 movs r2, #0
8000f68: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000f6a: 4b04 ldr r3, [pc, #16] ; (8000f7c <SysTick_Config+0x40>)
8000f6c: 2207 movs r2, #7
8000f6e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000f70: 2300 movs r3, #0
}
8000f72: 4618 mov r0, r3
8000f74: 3708 adds r7, #8
8000f76: 46bd mov sp, r7
8000f78: bd80 pop {r7, pc}
8000f7a: bf00 nop
8000f7c: e000e010 .word 0xe000e010
08000f80 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000f80: b580 push {r7, lr}
8000f82: b082 sub sp, #8
8000f84: af00 add r7, sp, #0
8000f86: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000f88: 6878 ldr r0, [r7, #4]
8000f8a: f7ff ff29 bl 8000de0 <__NVIC_SetPriorityGrouping>
}
8000f8e: bf00 nop
8000f90: 3708 adds r7, #8
8000f92: 46bd mov sp, r7
8000f94: bd80 pop {r7, pc}
08000f96 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000f96: b580 push {r7, lr}
8000f98: b086 sub sp, #24
8000f9a: af00 add r7, sp, #0
8000f9c: 4603 mov r3, r0
8000f9e: 60b9 str r1, [r7, #8]
8000fa0: 607a str r2, [r7, #4]
8000fa2: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000fa4: 2300 movs r3, #0
8000fa6: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000fa8: f7ff ff3e bl 8000e28 <__NVIC_GetPriorityGrouping>
8000fac: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000fae: 687a ldr r2, [r7, #4]
8000fb0: 68b9 ldr r1, [r7, #8]
8000fb2: 6978 ldr r0, [r7, #20]
8000fb4: f7ff ff8e bl 8000ed4 <NVIC_EncodePriority>
8000fb8: 4602 mov r2, r0
8000fba: f997 300f ldrsb.w r3, [r7, #15]
8000fbe: 4611 mov r1, r2
8000fc0: 4618 mov r0, r3
8000fc2: f7ff ff5d bl 8000e80 <__NVIC_SetPriority>
}
8000fc6: bf00 nop
8000fc8: 3718 adds r7, #24
8000fca: 46bd mov sp, r7
8000fcc: bd80 pop {r7, pc}
08000fce <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000fce: b580 push {r7, lr}
8000fd0: b082 sub sp, #8
8000fd2: af00 add r7, sp, #0
8000fd4: 4603 mov r3, r0
8000fd6: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000fd8: f997 3007 ldrsb.w r3, [r7, #7]
8000fdc: 4618 mov r0, r3
8000fde: f7ff ff31 bl 8000e44 <__NVIC_EnableIRQ>
}
8000fe2: bf00 nop
8000fe4: 3708 adds r7, #8
8000fe6: 46bd mov sp, r7
8000fe8: bd80 pop {r7, pc}
08000fea <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000fea: b580 push {r7, lr}
8000fec: b082 sub sp, #8
8000fee: af00 add r7, sp, #0
8000ff0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000ff2: 6878 ldr r0, [r7, #4]
8000ff4: f7ff ffa2 bl 8000f3c <SysTick_Config>
8000ff8: 4603 mov r3, r0
}
8000ffa: 4618 mov r0, r3
8000ffc: 3708 adds r7, #8
8000ffe: 46bd mov sp, r7
8001000: bd80 pop {r7, pc}
...
08001004 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001004: b480 push {r7}
8001006: b089 sub sp, #36 ; 0x24
8001008: af00 add r7, sp, #0
800100a: 6078 str r0, [r7, #4]
800100c: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
800100e: 2300 movs r3, #0
8001010: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8001012: 2300 movs r3, #0
8001014: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001016: 2300 movs r3, #0
8001018: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
800101a: 2300 movs r3, #0
800101c: 61fb str r3, [r7, #28]
800101e: e159 b.n 80012d4 <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
8001020: 2201 movs r2, #1
8001022: 69fb ldr r3, [r7, #28]
8001024: fa02 f303 lsl.w r3, r2, r3
8001028: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800102a: 683b ldr r3, [r7, #0]
800102c: 681b ldr r3, [r3, #0]
800102e: 697a ldr r2, [r7, #20]
8001030: 4013 ands r3, r2
8001032: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8001034: 693a ldr r2, [r7, #16]
8001036: 697b ldr r3, [r7, #20]
8001038: 429a cmp r2, r3
800103a: f040 8148 bne.w 80012ce <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
800103e: 683b ldr r3, [r7, #0]
8001040: 685b ldr r3, [r3, #4]
8001042: f003 0303 and.w r3, r3, #3
8001046: 2b01 cmp r3, #1
8001048: d005 beq.n 8001056 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800104a: 683b ldr r3, [r7, #0]
800104c: 685b ldr r3, [r3, #4]
800104e: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001052: 2b02 cmp r3, #2
8001054: d130 bne.n 80010b8 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001056: 687b ldr r3, [r7, #4]
8001058: 689b ldr r3, [r3, #8]
800105a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
800105c: 69fb ldr r3, [r7, #28]
800105e: 005b lsls r3, r3, #1
8001060: 2203 movs r2, #3
8001062: fa02 f303 lsl.w r3, r2, r3
8001066: 43db mvns r3, r3
8001068: 69ba ldr r2, [r7, #24]
800106a: 4013 ands r3, r2
800106c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
800106e: 683b ldr r3, [r7, #0]
8001070: 68da ldr r2, [r3, #12]
8001072: 69fb ldr r3, [r7, #28]
8001074: 005b lsls r3, r3, #1
8001076: fa02 f303 lsl.w r3, r2, r3
800107a: 69ba ldr r2, [r7, #24]
800107c: 4313 orrs r3, r2
800107e: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001080: 687b ldr r3, [r7, #4]
8001082: 69ba ldr r2, [r7, #24]
8001084: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001086: 687b ldr r3, [r7, #4]
8001088: 685b ldr r3, [r3, #4]
800108a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800108c: 2201 movs r2, #1
800108e: 69fb ldr r3, [r7, #28]
8001090: fa02 f303 lsl.w r3, r2, r3
8001094: 43db mvns r3, r3
8001096: 69ba ldr r2, [r7, #24]
8001098: 4013 ands r3, r2
800109a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800109c: 683b ldr r3, [r7, #0]
800109e: 685b ldr r3, [r3, #4]
80010a0: 091b lsrs r3, r3, #4
80010a2: f003 0201 and.w r2, r3, #1
80010a6: 69fb ldr r3, [r7, #28]
80010a8: fa02 f303 lsl.w r3, r2, r3
80010ac: 69ba ldr r2, [r7, #24]
80010ae: 4313 orrs r3, r2
80010b0: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
80010b2: 687b ldr r3, [r7, #4]
80010b4: 69ba ldr r2, [r7, #24]
80010b6: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80010b8: 683b ldr r3, [r7, #0]
80010ba: 685b ldr r3, [r3, #4]
80010bc: f003 0303 and.w r3, r3, #3
80010c0: 2b03 cmp r3, #3
80010c2: d017 beq.n 80010f4 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80010c4: 687b ldr r3, [r7, #4]
80010c6: 68db ldr r3, [r3, #12]
80010c8: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
80010ca: 69fb ldr r3, [r7, #28]
80010cc: 005b lsls r3, r3, #1
80010ce: 2203 movs r2, #3
80010d0: fa02 f303 lsl.w r3, r2, r3
80010d4: 43db mvns r3, r3
80010d6: 69ba ldr r2, [r7, #24]
80010d8: 4013 ands r3, r2
80010da: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80010dc: 683b ldr r3, [r7, #0]
80010de: 689a ldr r2, [r3, #8]
80010e0: 69fb ldr r3, [r7, #28]
80010e2: 005b lsls r3, r3, #1
80010e4: fa02 f303 lsl.w r3, r2, r3
80010e8: 69ba ldr r2, [r7, #24]
80010ea: 4313 orrs r3, r2
80010ec: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
80010ee: 687b ldr r3, [r7, #4]
80010f0: 69ba ldr r2, [r7, #24]
80010f2: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80010f4: 683b ldr r3, [r7, #0]
80010f6: 685b ldr r3, [r3, #4]
80010f8: f003 0303 and.w r3, r3, #3
80010fc: 2b02 cmp r3, #2
80010fe: d123 bne.n 8001148 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001100: 69fb ldr r3, [r7, #28]
8001102: 08da lsrs r2, r3, #3
8001104: 687b ldr r3, [r7, #4]
8001106: 3208 adds r2, #8
8001108: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800110c: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
800110e: 69fb ldr r3, [r7, #28]
8001110: f003 0307 and.w r3, r3, #7
8001114: 009b lsls r3, r3, #2
8001116: 220f movs r2, #15
8001118: fa02 f303 lsl.w r3, r2, r3
800111c: 43db mvns r3, r3
800111e: 69ba ldr r2, [r7, #24]
8001120: 4013 ands r3, r2
8001122: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8001124: 683b ldr r3, [r7, #0]
8001126: 691a ldr r2, [r3, #16]
8001128: 69fb ldr r3, [r7, #28]
800112a: f003 0307 and.w r3, r3, #7
800112e: 009b lsls r3, r3, #2
8001130: fa02 f303 lsl.w r3, r2, r3
8001134: 69ba ldr r2, [r7, #24]
8001136: 4313 orrs r3, r2
8001138: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
800113a: 69fb ldr r3, [r7, #28]
800113c: 08da lsrs r2, r3, #3
800113e: 687b ldr r3, [r7, #4]
8001140: 3208 adds r2, #8
8001142: 69b9 ldr r1, [r7, #24]
8001144: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001148: 687b ldr r3, [r7, #4]
800114a: 681b ldr r3, [r3, #0]
800114c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
800114e: 69fb ldr r3, [r7, #28]
8001150: 005b lsls r3, r3, #1
8001152: 2203 movs r2, #3
8001154: fa02 f303 lsl.w r3, r2, r3
8001158: 43db mvns r3, r3
800115a: 69ba ldr r2, [r7, #24]
800115c: 4013 ands r3, r2
800115e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001160: 683b ldr r3, [r7, #0]
8001162: 685b ldr r3, [r3, #4]
8001164: f003 0203 and.w r2, r3, #3
8001168: 69fb ldr r3, [r7, #28]
800116a: 005b lsls r3, r3, #1
800116c: fa02 f303 lsl.w r3, r2, r3
8001170: 69ba ldr r2, [r7, #24]
8001172: 4313 orrs r3, r2
8001174: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001176: 687b ldr r3, [r7, #4]
8001178: 69ba ldr r2, [r7, #24]
800117a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
800117c: 683b ldr r3, [r7, #0]
800117e: 685b ldr r3, [r3, #4]
8001180: f403 3340 and.w r3, r3, #196608 ; 0x30000
8001184: 2b00 cmp r3, #0
8001186: f000 80a2 beq.w 80012ce <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800118a: 2300 movs r3, #0
800118c: 60fb str r3, [r7, #12]
800118e: 4b57 ldr r3, [pc, #348] ; (80012ec <HAL_GPIO_Init+0x2e8>)
8001190: 6c5b ldr r3, [r3, #68] ; 0x44
8001192: 4a56 ldr r2, [pc, #344] ; (80012ec <HAL_GPIO_Init+0x2e8>)
8001194: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001198: 6453 str r3, [r2, #68] ; 0x44
800119a: 4b54 ldr r3, [pc, #336] ; (80012ec <HAL_GPIO_Init+0x2e8>)
800119c: 6c5b ldr r3, [r3, #68] ; 0x44
800119e: f403 4380 and.w r3, r3, #16384 ; 0x4000
80011a2: 60fb str r3, [r7, #12]
80011a4: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
80011a6: 4a52 ldr r2, [pc, #328] ; (80012f0 <HAL_GPIO_Init+0x2ec>)
80011a8: 69fb ldr r3, [r7, #28]
80011aa: 089b lsrs r3, r3, #2
80011ac: 3302 adds r3, #2
80011ae: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80011b2: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
80011b4: 69fb ldr r3, [r7, #28]
80011b6: f003 0303 and.w r3, r3, #3
80011ba: 009b lsls r3, r3, #2
80011bc: 220f movs r2, #15
80011be: fa02 f303 lsl.w r3, r2, r3
80011c2: 43db mvns r3, r3
80011c4: 69ba ldr r2, [r7, #24]
80011c6: 4013 ands r3, r2
80011c8: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
80011ca: 687b ldr r3, [r7, #4]
80011cc: 4a49 ldr r2, [pc, #292] ; (80012f4 <HAL_GPIO_Init+0x2f0>)
80011ce: 4293 cmp r3, r2
80011d0: d019 beq.n 8001206 <HAL_GPIO_Init+0x202>
80011d2: 687b ldr r3, [r7, #4]
80011d4: 4a48 ldr r2, [pc, #288] ; (80012f8 <HAL_GPIO_Init+0x2f4>)
80011d6: 4293 cmp r3, r2
80011d8: d013 beq.n 8001202 <HAL_GPIO_Init+0x1fe>
80011da: 687b ldr r3, [r7, #4]
80011dc: 4a47 ldr r2, [pc, #284] ; (80012fc <HAL_GPIO_Init+0x2f8>)
80011de: 4293 cmp r3, r2
80011e0: d00d beq.n 80011fe <HAL_GPIO_Init+0x1fa>
80011e2: 687b ldr r3, [r7, #4]
80011e4: 4a46 ldr r2, [pc, #280] ; (8001300 <HAL_GPIO_Init+0x2fc>)
80011e6: 4293 cmp r3, r2
80011e8: d007 beq.n 80011fa <HAL_GPIO_Init+0x1f6>
80011ea: 687b ldr r3, [r7, #4]
80011ec: 4a45 ldr r2, [pc, #276] ; (8001304 <HAL_GPIO_Init+0x300>)
80011ee: 4293 cmp r3, r2
80011f0: d101 bne.n 80011f6 <HAL_GPIO_Init+0x1f2>
80011f2: 2304 movs r3, #4
80011f4: e008 b.n 8001208 <HAL_GPIO_Init+0x204>
80011f6: 2307 movs r3, #7
80011f8: e006 b.n 8001208 <HAL_GPIO_Init+0x204>
80011fa: 2303 movs r3, #3
80011fc: e004 b.n 8001208 <HAL_GPIO_Init+0x204>
80011fe: 2302 movs r3, #2
8001200: e002 b.n 8001208 <HAL_GPIO_Init+0x204>
8001202: 2301 movs r3, #1
8001204: e000 b.n 8001208 <HAL_GPIO_Init+0x204>
8001206: 2300 movs r3, #0
8001208: 69fa ldr r2, [r7, #28]
800120a: f002 0203 and.w r2, r2, #3
800120e: 0092 lsls r2, r2, #2
8001210: 4093 lsls r3, r2
8001212: 69ba ldr r2, [r7, #24]
8001214: 4313 orrs r3, r2
8001216: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001218: 4935 ldr r1, [pc, #212] ; (80012f0 <HAL_GPIO_Init+0x2ec>)
800121a: 69fb ldr r3, [r7, #28]
800121c: 089b lsrs r3, r3, #2
800121e: 3302 adds r3, #2
8001220: 69ba ldr r2, [r7, #24]
8001222: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001226: 4b38 ldr r3, [pc, #224] ; (8001308 <HAL_GPIO_Init+0x304>)
8001228: 689b ldr r3, [r3, #8]
800122a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800122c: 693b ldr r3, [r7, #16]
800122e: 43db mvns r3, r3
8001230: 69ba ldr r2, [r7, #24]
8001232: 4013 ands r3, r2
8001234: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001236: 683b ldr r3, [r7, #0]
8001238: 685b ldr r3, [r3, #4]
800123a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800123e: 2b00 cmp r3, #0
8001240: d003 beq.n 800124a <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
8001242: 69ba ldr r2, [r7, #24]
8001244: 693b ldr r3, [r7, #16]
8001246: 4313 orrs r3, r2
8001248: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
800124a: 4a2f ldr r2, [pc, #188] ; (8001308 <HAL_GPIO_Init+0x304>)
800124c: 69bb ldr r3, [r7, #24]
800124e: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001250: 4b2d ldr r3, [pc, #180] ; (8001308 <HAL_GPIO_Init+0x304>)
8001252: 68db ldr r3, [r3, #12]
8001254: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001256: 693b ldr r3, [r7, #16]
8001258: 43db mvns r3, r3
800125a: 69ba ldr r2, [r7, #24]
800125c: 4013 ands r3, r2
800125e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001260: 683b ldr r3, [r7, #0]
8001262: 685b ldr r3, [r3, #4]
8001264: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001268: 2b00 cmp r3, #0
800126a: d003 beq.n 8001274 <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
800126c: 69ba ldr r2, [r7, #24]
800126e: 693b ldr r3, [r7, #16]
8001270: 4313 orrs r3, r2
8001272: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001274: 4a24 ldr r2, [pc, #144] ; (8001308 <HAL_GPIO_Init+0x304>)
8001276: 69bb ldr r3, [r7, #24]
8001278: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
800127a: 4b23 ldr r3, [pc, #140] ; (8001308 <HAL_GPIO_Init+0x304>)
800127c: 685b ldr r3, [r3, #4]
800127e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001280: 693b ldr r3, [r7, #16]
8001282: 43db mvns r3, r3
8001284: 69ba ldr r2, [r7, #24]
8001286: 4013 ands r3, r2
8001288: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
800128a: 683b ldr r3, [r7, #0]
800128c: 685b ldr r3, [r3, #4]
800128e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001292: 2b00 cmp r3, #0
8001294: d003 beq.n 800129e <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
8001296: 69ba ldr r2, [r7, #24]
8001298: 693b ldr r3, [r7, #16]
800129a: 4313 orrs r3, r2
800129c: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
800129e: 4a1a ldr r2, [pc, #104] ; (8001308 <HAL_GPIO_Init+0x304>)
80012a0: 69bb ldr r3, [r7, #24]
80012a2: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80012a4: 4b18 ldr r3, [pc, #96] ; (8001308 <HAL_GPIO_Init+0x304>)
80012a6: 681b ldr r3, [r3, #0]
80012a8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80012aa: 693b ldr r3, [r7, #16]
80012ac: 43db mvns r3, r3
80012ae: 69ba ldr r2, [r7, #24]
80012b0: 4013 ands r3, r2
80012b2: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80012b4: 683b ldr r3, [r7, #0]
80012b6: 685b ldr r3, [r3, #4]
80012b8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80012bc: 2b00 cmp r3, #0
80012be: d003 beq.n 80012c8 <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
80012c0: 69ba ldr r2, [r7, #24]
80012c2: 693b ldr r3, [r7, #16]
80012c4: 4313 orrs r3, r2
80012c6: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80012c8: 4a0f ldr r2, [pc, #60] ; (8001308 <HAL_GPIO_Init+0x304>)
80012ca: 69bb ldr r3, [r7, #24]
80012cc: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
80012ce: 69fb ldr r3, [r7, #28]
80012d0: 3301 adds r3, #1
80012d2: 61fb str r3, [r7, #28]
80012d4: 69fb ldr r3, [r7, #28]
80012d6: 2b0f cmp r3, #15
80012d8: f67f aea2 bls.w 8001020 <HAL_GPIO_Init+0x1c>
}
}
}
}
80012dc: bf00 nop
80012de: bf00 nop
80012e0: 3724 adds r7, #36 ; 0x24
80012e2: 46bd mov sp, r7
80012e4: f85d 7b04 ldr.w r7, [sp], #4
80012e8: 4770 bx lr
80012ea: bf00 nop
80012ec: 40023800 .word 0x40023800
80012f0: 40013800 .word 0x40013800
80012f4: 40020000 .word 0x40020000
80012f8: 40020400 .word 0x40020400
80012fc: 40020800 .word 0x40020800
8001300: 40020c00 .word 0x40020c00
8001304: 40021000 .word 0x40021000
8001308: 40013c00 .word 0x40013c00
0800130c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800130c: b480 push {r7}
800130e: b083 sub sp, #12
8001310: af00 add r7, sp, #0
8001312: 6078 str r0, [r7, #4]
8001314: 460b mov r3, r1
8001316: 807b strh r3, [r7, #2]
8001318: 4613 mov r3, r2
800131a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
800131c: 787b ldrb r3, [r7, #1]
800131e: 2b00 cmp r3, #0
8001320: d003 beq.n 800132a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001322: 887a ldrh r2, [r7, #2]
8001324: 687b ldr r3, [r7, #4]
8001326: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001328: e003 b.n 8001332 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
800132a: 887b ldrh r3, [r7, #2]
800132c: 041a lsls r2, r3, #16
800132e: 687b ldr r3, [r7, #4]
8001330: 619a str r2, [r3, #24]
}
8001332: bf00 nop
8001334: 370c adds r7, #12
8001336: 46bd mov sp, r7
8001338: f85d 7b04 ldr.w r7, [sp], #4
800133c: 4770 bx lr
0800133e <HAL_GPIO_TogglePin>:
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
800133e: b480 push {r7}
8001340: b085 sub sp, #20
8001342: af00 add r7, sp, #0
8001344: 6078 str r0, [r7, #4]
8001346: 460b mov r3, r1
8001348: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
800134a: 687b ldr r3, [r7, #4]
800134c: 695b ldr r3, [r3, #20]
800134e: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001350: 887a ldrh r2, [r7, #2]
8001352: 68fb ldr r3, [r7, #12]
8001354: 4013 ands r3, r2
8001356: 041a lsls r2, r3, #16
8001358: 68fb ldr r3, [r7, #12]
800135a: 43d9 mvns r1, r3
800135c: 887b ldrh r3, [r7, #2]
800135e: 400b ands r3, r1
8001360: 431a orrs r2, r3
8001362: 687b ldr r3, [r7, #4]
8001364: 619a str r2, [r3, #24]
}
8001366: bf00 nop
8001368: 3714 adds r7, #20
800136a: 46bd mov sp, r7
800136c: f85d 7b04 ldr.w r7, [sp], #4
8001370: 4770 bx lr
...
08001374 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001374: b580 push {r7, lr}
8001376: b086 sub sp, #24
8001378: af00 add r7, sp, #0
800137a: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
800137c: 687b ldr r3, [r7, #4]
800137e: 2b00 cmp r3, #0
8001380: d101 bne.n 8001386 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8001382: 2301 movs r3, #1
8001384: e267 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001386: 687b ldr r3, [r7, #4]
8001388: 681b ldr r3, [r3, #0]
800138a: f003 0301 and.w r3, r3, #1
800138e: 2b00 cmp r3, #0
8001390: d075 beq.n 800147e <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8001392: 4b88 ldr r3, [pc, #544] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001394: 689b ldr r3, [r3, #8]
8001396: f003 030c and.w r3, r3, #12
800139a: 2b04 cmp r3, #4
800139c: d00c beq.n 80013b8 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
800139e: 4b85 ldr r3, [pc, #532] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013a0: 689b ldr r3, [r3, #8]
80013a2: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80013a6: 2b08 cmp r3, #8
80013a8: d112 bne.n 80013d0 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80013aa: 4b82 ldr r3, [pc, #520] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013ac: 685b ldr r3, [r3, #4]
80013ae: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80013b2: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80013b6: d10b bne.n 80013d0 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80013b8: 4b7e ldr r3, [pc, #504] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013ba: 681b ldr r3, [r3, #0]
80013bc: f403 3300 and.w r3, r3, #131072 ; 0x20000
80013c0: 2b00 cmp r3, #0
80013c2: d05b beq.n 800147c <HAL_RCC_OscConfig+0x108>
80013c4: 687b ldr r3, [r7, #4]
80013c6: 685b ldr r3, [r3, #4]
80013c8: 2b00 cmp r3, #0
80013ca: d157 bne.n 800147c <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80013cc: 2301 movs r3, #1
80013ce: e242 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80013d0: 687b ldr r3, [r7, #4]
80013d2: 685b ldr r3, [r3, #4]
80013d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80013d8: d106 bne.n 80013e8 <HAL_RCC_OscConfig+0x74>
80013da: 4b76 ldr r3, [pc, #472] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013dc: 681b ldr r3, [r3, #0]
80013de: 4a75 ldr r2, [pc, #468] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013e0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80013e4: 6013 str r3, [r2, #0]
80013e6: e01d b.n 8001424 <HAL_RCC_OscConfig+0xb0>
80013e8: 687b ldr r3, [r7, #4]
80013ea: 685b ldr r3, [r3, #4]
80013ec: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80013f0: d10c bne.n 800140c <HAL_RCC_OscConfig+0x98>
80013f2: 4b70 ldr r3, [pc, #448] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013f4: 681b ldr r3, [r3, #0]
80013f6: 4a6f ldr r2, [pc, #444] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80013f8: f443 2380 orr.w r3, r3, #262144 ; 0x40000
80013fc: 6013 str r3, [r2, #0]
80013fe: 4b6d ldr r3, [pc, #436] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001400: 681b ldr r3, [r3, #0]
8001402: 4a6c ldr r2, [pc, #432] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001404: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001408: 6013 str r3, [r2, #0]
800140a: e00b b.n 8001424 <HAL_RCC_OscConfig+0xb0>
800140c: 4b69 ldr r3, [pc, #420] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
800140e: 681b ldr r3, [r3, #0]
8001410: 4a68 ldr r2, [pc, #416] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001412: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001416: 6013 str r3, [r2, #0]
8001418: 4b66 ldr r3, [pc, #408] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
800141a: 681b ldr r3, [r3, #0]
800141c: 4a65 ldr r2, [pc, #404] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
800141e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8001422: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8001424: 687b ldr r3, [r7, #4]
8001426: 685b ldr r3, [r3, #4]
8001428: 2b00 cmp r3, #0
800142a: d013 beq.n 8001454 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800142c: f7ff fccc bl 8000dc8 <HAL_GetTick>
8001430: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001432: e008 b.n 8001446 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001434: f7ff fcc8 bl 8000dc8 <HAL_GetTick>
8001438: 4602 mov r2, r0
800143a: 693b ldr r3, [r7, #16]
800143c: 1ad3 subs r3, r2, r3
800143e: 2b64 cmp r3, #100 ; 0x64
8001440: d901 bls.n 8001446 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8001442: 2303 movs r3, #3
8001444: e207 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001446: 4b5b ldr r3, [pc, #364] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001448: 681b ldr r3, [r3, #0]
800144a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800144e: 2b00 cmp r3, #0
8001450: d0f0 beq.n 8001434 <HAL_RCC_OscConfig+0xc0>
8001452: e014 b.n 800147e <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001454: f7ff fcb8 bl 8000dc8 <HAL_GetTick>
8001458: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800145a: e008 b.n 800146e <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800145c: f7ff fcb4 bl 8000dc8 <HAL_GetTick>
8001460: 4602 mov r2, r0
8001462: 693b ldr r3, [r7, #16]
8001464: 1ad3 subs r3, r2, r3
8001466: 2b64 cmp r3, #100 ; 0x64
8001468: d901 bls.n 800146e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800146a: 2303 movs r3, #3
800146c: e1f3 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800146e: 4b51 ldr r3, [pc, #324] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001470: 681b ldr r3, [r3, #0]
8001472: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001476: 2b00 cmp r3, #0
8001478: d1f0 bne.n 800145c <HAL_RCC_OscConfig+0xe8>
800147a: e000 b.n 800147e <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800147c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800147e: 687b ldr r3, [r7, #4]
8001480: 681b ldr r3, [r3, #0]
8001482: f003 0302 and.w r3, r3, #2
8001486: 2b00 cmp r3, #0
8001488: d063 beq.n 8001552 <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
800148a: 4b4a ldr r3, [pc, #296] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
800148c: 689b ldr r3, [r3, #8]
800148e: f003 030c and.w r3, r3, #12
8001492: 2b00 cmp r3, #0
8001494: d00b beq.n 80014ae <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001496: 4b47 ldr r3, [pc, #284] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001498: 689b ldr r3, [r3, #8]
800149a: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
800149e: 2b08 cmp r3, #8
80014a0: d11c bne.n 80014dc <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80014a2: 4b44 ldr r3, [pc, #272] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80014a4: 685b ldr r3, [r3, #4]
80014a6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80014aa: 2b00 cmp r3, #0
80014ac: d116 bne.n 80014dc <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014ae: 4b41 ldr r3, [pc, #260] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80014b0: 681b ldr r3, [r3, #0]
80014b2: f003 0302 and.w r3, r3, #2
80014b6: 2b00 cmp r3, #0
80014b8: d005 beq.n 80014c6 <HAL_RCC_OscConfig+0x152>
80014ba: 687b ldr r3, [r7, #4]
80014bc: 68db ldr r3, [r3, #12]
80014be: 2b01 cmp r3, #1
80014c0: d001 beq.n 80014c6 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80014c2: 2301 movs r3, #1
80014c4: e1c7 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80014c6: 4b3b ldr r3, [pc, #236] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80014c8: 681b ldr r3, [r3, #0]
80014ca: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80014ce: 687b ldr r3, [r7, #4]
80014d0: 691b ldr r3, [r3, #16]
80014d2: 00db lsls r3, r3, #3
80014d4: 4937 ldr r1, [pc, #220] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
80014d6: 4313 orrs r3, r2
80014d8: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014da: e03a b.n 8001552 <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
80014dc: 687b ldr r3, [r7, #4]
80014de: 68db ldr r3, [r3, #12]
80014e0: 2b00 cmp r3, #0
80014e2: d020 beq.n 8001526 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80014e4: 4b34 ldr r3, [pc, #208] ; (80015b8 <HAL_RCC_OscConfig+0x244>)
80014e6: 2201 movs r2, #1
80014e8: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80014ea: f7ff fc6d bl 8000dc8 <HAL_GetTick>
80014ee: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80014f0: e008 b.n 8001504 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80014f2: f7ff fc69 bl 8000dc8 <HAL_GetTick>
80014f6: 4602 mov r2, r0
80014f8: 693b ldr r3, [r7, #16]
80014fa: 1ad3 subs r3, r2, r3
80014fc: 2b02 cmp r3, #2
80014fe: d901 bls.n 8001504 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8001500: 2303 movs r3, #3
8001502: e1a8 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001504: 4b2b ldr r3, [pc, #172] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001506: 681b ldr r3, [r3, #0]
8001508: f003 0302 and.w r3, r3, #2
800150c: 2b00 cmp r3, #0
800150e: d0f0 beq.n 80014f2 <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001510: 4b28 ldr r3, [pc, #160] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001512: 681b ldr r3, [r3, #0]
8001514: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001518: 687b ldr r3, [r7, #4]
800151a: 691b ldr r3, [r3, #16]
800151c: 00db lsls r3, r3, #3
800151e: 4925 ldr r1, [pc, #148] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001520: 4313 orrs r3, r2
8001522: 600b str r3, [r1, #0]
8001524: e015 b.n 8001552 <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001526: 4b24 ldr r3, [pc, #144] ; (80015b8 <HAL_RCC_OscConfig+0x244>)
8001528: 2200 movs r2, #0
800152a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800152c: f7ff fc4c bl 8000dc8 <HAL_GetTick>
8001530: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001532: e008 b.n 8001546 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001534: f7ff fc48 bl 8000dc8 <HAL_GetTick>
8001538: 4602 mov r2, r0
800153a: 693b ldr r3, [r7, #16]
800153c: 1ad3 subs r3, r2, r3
800153e: 2b02 cmp r3, #2
8001540: d901 bls.n 8001546 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8001542: 2303 movs r3, #3
8001544: e187 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001546: 4b1b ldr r3, [pc, #108] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001548: 681b ldr r3, [r3, #0]
800154a: f003 0302 and.w r3, r3, #2
800154e: 2b00 cmp r3, #0
8001550: d1f0 bne.n 8001534 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001552: 687b ldr r3, [r7, #4]
8001554: 681b ldr r3, [r3, #0]
8001556: f003 0308 and.w r3, r3, #8
800155a: 2b00 cmp r3, #0
800155c: d036 beq.n 80015cc <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
800155e: 687b ldr r3, [r7, #4]
8001560: 695b ldr r3, [r3, #20]
8001562: 2b00 cmp r3, #0
8001564: d016 beq.n 8001594 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001566: 4b15 ldr r3, [pc, #84] ; (80015bc <HAL_RCC_OscConfig+0x248>)
8001568: 2201 movs r2, #1
800156a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800156c: f7ff fc2c bl 8000dc8 <HAL_GetTick>
8001570: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001572: e008 b.n 8001586 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001574: f7ff fc28 bl 8000dc8 <HAL_GetTick>
8001578: 4602 mov r2, r0
800157a: 693b ldr r3, [r7, #16]
800157c: 1ad3 subs r3, r2, r3
800157e: 2b02 cmp r3, #2
8001580: d901 bls.n 8001586 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8001582: 2303 movs r3, #3
8001584: e167 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001586: 4b0b ldr r3, [pc, #44] ; (80015b4 <HAL_RCC_OscConfig+0x240>)
8001588: 6f5b ldr r3, [r3, #116] ; 0x74
800158a: f003 0302 and.w r3, r3, #2
800158e: 2b00 cmp r3, #0
8001590: d0f0 beq.n 8001574 <HAL_RCC_OscConfig+0x200>
8001592: e01b b.n 80015cc <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001594: 4b09 ldr r3, [pc, #36] ; (80015bc <HAL_RCC_OscConfig+0x248>)
8001596: 2200 movs r2, #0
8001598: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800159a: f7ff fc15 bl 8000dc8 <HAL_GetTick>
800159e: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80015a0: e00e b.n 80015c0 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80015a2: f7ff fc11 bl 8000dc8 <HAL_GetTick>
80015a6: 4602 mov r2, r0
80015a8: 693b ldr r3, [r7, #16]
80015aa: 1ad3 subs r3, r2, r3
80015ac: 2b02 cmp r3, #2
80015ae: d907 bls.n 80015c0 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80015b0: 2303 movs r3, #3
80015b2: e150 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
80015b4: 40023800 .word 0x40023800
80015b8: 42470000 .word 0x42470000
80015bc: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80015c0: 4b88 ldr r3, [pc, #544] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80015c2: 6f5b ldr r3, [r3, #116] ; 0x74
80015c4: f003 0302 and.w r3, r3, #2
80015c8: 2b00 cmp r3, #0
80015ca: d1ea bne.n 80015a2 <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80015cc: 687b ldr r3, [r7, #4]
80015ce: 681b ldr r3, [r3, #0]
80015d0: f003 0304 and.w r3, r3, #4
80015d4: 2b00 cmp r3, #0
80015d6: f000 8097 beq.w 8001708 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
80015da: 2300 movs r3, #0
80015dc: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80015de: 4b81 ldr r3, [pc, #516] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80015e0: 6c1b ldr r3, [r3, #64] ; 0x40
80015e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80015e6: 2b00 cmp r3, #0
80015e8: d10f bne.n 800160a <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
80015ea: 2300 movs r3, #0
80015ec: 60bb str r3, [r7, #8]
80015ee: 4b7d ldr r3, [pc, #500] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80015f0: 6c1b ldr r3, [r3, #64] ; 0x40
80015f2: 4a7c ldr r2, [pc, #496] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80015f4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80015f8: 6413 str r3, [r2, #64] ; 0x40
80015fa: 4b7a ldr r3, [pc, #488] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80015fc: 6c1b ldr r3, [r3, #64] ; 0x40
80015fe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001602: 60bb str r3, [r7, #8]
8001604: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001606: 2301 movs r3, #1
8001608: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800160a: 4b77 ldr r3, [pc, #476] ; (80017e8 <HAL_RCC_OscConfig+0x474>)
800160c: 681b ldr r3, [r3, #0]
800160e: f403 7380 and.w r3, r3, #256 ; 0x100
8001612: 2b00 cmp r3, #0
8001614: d118 bne.n 8001648 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001616: 4b74 ldr r3, [pc, #464] ; (80017e8 <HAL_RCC_OscConfig+0x474>)
8001618: 681b ldr r3, [r3, #0]
800161a: 4a73 ldr r2, [pc, #460] ; (80017e8 <HAL_RCC_OscConfig+0x474>)
800161c: f443 7380 orr.w r3, r3, #256 ; 0x100
8001620: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001622: f7ff fbd1 bl 8000dc8 <HAL_GetTick>
8001626: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001628: e008 b.n 800163c <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800162a: f7ff fbcd bl 8000dc8 <HAL_GetTick>
800162e: 4602 mov r2, r0
8001630: 693b ldr r3, [r7, #16]
8001632: 1ad3 subs r3, r2, r3
8001634: 2b02 cmp r3, #2
8001636: d901 bls.n 800163c <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001638: 2303 movs r3, #3
800163a: e10c b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800163c: 4b6a ldr r3, [pc, #424] ; (80017e8 <HAL_RCC_OscConfig+0x474>)
800163e: 681b ldr r3, [r3, #0]
8001640: f403 7380 and.w r3, r3, #256 ; 0x100
8001644: 2b00 cmp r3, #0
8001646: d0f0 beq.n 800162a <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001648: 687b ldr r3, [r7, #4]
800164a: 689b ldr r3, [r3, #8]
800164c: 2b01 cmp r3, #1
800164e: d106 bne.n 800165e <HAL_RCC_OscConfig+0x2ea>
8001650: 4b64 ldr r3, [pc, #400] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001652: 6f1b ldr r3, [r3, #112] ; 0x70
8001654: 4a63 ldr r2, [pc, #396] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001656: f043 0301 orr.w r3, r3, #1
800165a: 6713 str r3, [r2, #112] ; 0x70
800165c: e01c b.n 8001698 <HAL_RCC_OscConfig+0x324>
800165e: 687b ldr r3, [r7, #4]
8001660: 689b ldr r3, [r3, #8]
8001662: 2b05 cmp r3, #5
8001664: d10c bne.n 8001680 <HAL_RCC_OscConfig+0x30c>
8001666: 4b5f ldr r3, [pc, #380] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001668: 6f1b ldr r3, [r3, #112] ; 0x70
800166a: 4a5e ldr r2, [pc, #376] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
800166c: f043 0304 orr.w r3, r3, #4
8001670: 6713 str r3, [r2, #112] ; 0x70
8001672: 4b5c ldr r3, [pc, #368] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001674: 6f1b ldr r3, [r3, #112] ; 0x70
8001676: 4a5b ldr r2, [pc, #364] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001678: f043 0301 orr.w r3, r3, #1
800167c: 6713 str r3, [r2, #112] ; 0x70
800167e: e00b b.n 8001698 <HAL_RCC_OscConfig+0x324>
8001680: 4b58 ldr r3, [pc, #352] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001682: 6f1b ldr r3, [r3, #112] ; 0x70
8001684: 4a57 ldr r2, [pc, #348] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001686: f023 0301 bic.w r3, r3, #1
800168a: 6713 str r3, [r2, #112] ; 0x70
800168c: 4b55 ldr r3, [pc, #340] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
800168e: 6f1b ldr r3, [r3, #112] ; 0x70
8001690: 4a54 ldr r2, [pc, #336] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001692: f023 0304 bic.w r3, r3, #4
8001696: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001698: 687b ldr r3, [r7, #4]
800169a: 689b ldr r3, [r3, #8]
800169c: 2b00 cmp r3, #0
800169e: d015 beq.n 80016cc <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80016a0: f7ff fb92 bl 8000dc8 <HAL_GetTick>
80016a4: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80016a6: e00a b.n 80016be <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80016a8: f7ff fb8e bl 8000dc8 <HAL_GetTick>
80016ac: 4602 mov r2, r0
80016ae: 693b ldr r3, [r7, #16]
80016b0: 1ad3 subs r3, r2, r3
80016b2: f241 3288 movw r2, #5000 ; 0x1388
80016b6: 4293 cmp r3, r2
80016b8: d901 bls.n 80016be <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
80016ba: 2303 movs r3, #3
80016bc: e0cb b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80016be: 4b49 ldr r3, [pc, #292] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80016c0: 6f1b ldr r3, [r3, #112] ; 0x70
80016c2: f003 0302 and.w r3, r3, #2
80016c6: 2b00 cmp r3, #0
80016c8: d0ee beq.n 80016a8 <HAL_RCC_OscConfig+0x334>
80016ca: e014 b.n 80016f6 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80016cc: f7ff fb7c bl 8000dc8 <HAL_GetTick>
80016d0: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80016d2: e00a b.n 80016ea <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80016d4: f7ff fb78 bl 8000dc8 <HAL_GetTick>
80016d8: 4602 mov r2, r0
80016da: 693b ldr r3, [r7, #16]
80016dc: 1ad3 subs r3, r2, r3
80016de: f241 3288 movw r2, #5000 ; 0x1388
80016e2: 4293 cmp r3, r2
80016e4: d901 bls.n 80016ea <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
80016e6: 2303 movs r3, #3
80016e8: e0b5 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80016ea: 4b3e ldr r3, [pc, #248] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80016ec: 6f1b ldr r3, [r3, #112] ; 0x70
80016ee: f003 0302 and.w r3, r3, #2
80016f2: 2b00 cmp r3, #0
80016f4: d1ee bne.n 80016d4 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
80016f6: 7dfb ldrb r3, [r7, #23]
80016f8: 2b01 cmp r3, #1
80016fa: d105 bne.n 8001708 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
80016fc: 4b39 ldr r3, [pc, #228] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80016fe: 6c1b ldr r3, [r3, #64] ; 0x40
8001700: 4a38 ldr r2, [pc, #224] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001702: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001706: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001708: 687b ldr r3, [r7, #4]
800170a: 699b ldr r3, [r3, #24]
800170c: 2b00 cmp r3, #0
800170e: f000 80a1 beq.w 8001854 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8001712: 4b34 ldr r3, [pc, #208] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001714: 689b ldr r3, [r3, #8]
8001716: f003 030c and.w r3, r3, #12
800171a: 2b08 cmp r3, #8
800171c: d05c beq.n 80017d8 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800171e: 687b ldr r3, [r7, #4]
8001720: 699b ldr r3, [r3, #24]
8001722: 2b02 cmp r3, #2
8001724: d141 bne.n 80017aa <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001726: 4b31 ldr r3, [pc, #196] ; (80017ec <HAL_RCC_OscConfig+0x478>)
8001728: 2200 movs r2, #0
800172a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800172c: f7ff fb4c bl 8000dc8 <HAL_GetTick>
8001730: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001732: e008 b.n 8001746 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001734: f7ff fb48 bl 8000dc8 <HAL_GetTick>
8001738: 4602 mov r2, r0
800173a: 693b ldr r3, [r7, #16]
800173c: 1ad3 subs r3, r2, r3
800173e: 2b02 cmp r3, #2
8001740: d901 bls.n 8001746 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
8001742: 2303 movs r3, #3
8001744: e087 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001746: 4b27 ldr r3, [pc, #156] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001748: 681b ldr r3, [r3, #0]
800174a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800174e: 2b00 cmp r3, #0
8001750: d1f0 bne.n 8001734 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8001752: 687b ldr r3, [r7, #4]
8001754: 69da ldr r2, [r3, #28]
8001756: 687b ldr r3, [r7, #4]
8001758: 6a1b ldr r3, [r3, #32]
800175a: 431a orrs r2, r3
800175c: 687b ldr r3, [r7, #4]
800175e: 6a5b ldr r3, [r3, #36] ; 0x24
8001760: 019b lsls r3, r3, #6
8001762: 431a orrs r2, r3
8001764: 687b ldr r3, [r7, #4]
8001766: 6a9b ldr r3, [r3, #40] ; 0x28
8001768: 085b lsrs r3, r3, #1
800176a: 3b01 subs r3, #1
800176c: 041b lsls r3, r3, #16
800176e: 431a orrs r2, r3
8001770: 687b ldr r3, [r7, #4]
8001772: 6adb ldr r3, [r3, #44] ; 0x2c
8001774: 061b lsls r3, r3, #24
8001776: 491b ldr r1, [pc, #108] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
8001778: 4313 orrs r3, r2
800177a: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800177c: 4b1b ldr r3, [pc, #108] ; (80017ec <HAL_RCC_OscConfig+0x478>)
800177e: 2201 movs r2, #1
8001780: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001782: f7ff fb21 bl 8000dc8 <HAL_GetTick>
8001786: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001788: e008 b.n 800179c <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800178a: f7ff fb1d bl 8000dc8 <HAL_GetTick>
800178e: 4602 mov r2, r0
8001790: 693b ldr r3, [r7, #16]
8001792: 1ad3 subs r3, r2, r3
8001794: 2b02 cmp r3, #2
8001796: d901 bls.n 800179c <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
8001798: 2303 movs r3, #3
800179a: e05c b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800179c: 4b11 ldr r3, [pc, #68] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
800179e: 681b ldr r3, [r3, #0]
80017a0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80017a4: 2b00 cmp r3, #0
80017a6: d0f0 beq.n 800178a <HAL_RCC_OscConfig+0x416>
80017a8: e054 b.n 8001854 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80017aa: 4b10 ldr r3, [pc, #64] ; (80017ec <HAL_RCC_OscConfig+0x478>)
80017ac: 2200 movs r2, #0
80017ae: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80017b0: f7ff fb0a bl 8000dc8 <HAL_GetTick>
80017b4: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80017b6: e008 b.n 80017ca <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80017b8: f7ff fb06 bl 8000dc8 <HAL_GetTick>
80017bc: 4602 mov r2, r0
80017be: 693b ldr r3, [r7, #16]
80017c0: 1ad3 subs r3, r2, r3
80017c2: 2b02 cmp r3, #2
80017c4: d901 bls.n 80017ca <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
80017c6: 2303 movs r3, #3
80017c8: e045 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80017ca: 4b06 ldr r3, [pc, #24] ; (80017e4 <HAL_RCC_OscConfig+0x470>)
80017cc: 681b ldr r3, [r3, #0]
80017ce: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80017d2: 2b00 cmp r3, #0
80017d4: d1f0 bne.n 80017b8 <HAL_RCC_OscConfig+0x444>
80017d6: e03d b.n 8001854 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80017d8: 687b ldr r3, [r7, #4]
80017da: 699b ldr r3, [r3, #24]
80017dc: 2b01 cmp r3, #1
80017de: d107 bne.n 80017f0 <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
80017e0: 2301 movs r3, #1
80017e2: e038 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
80017e4: 40023800 .word 0x40023800
80017e8: 40007000 .word 0x40007000
80017ec: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
80017f0: 4b1b ldr r3, [pc, #108] ; (8001860 <HAL_RCC_OscConfig+0x4ec>)
80017f2: 685b ldr r3, [r3, #4]
80017f4: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80017f6: 687b ldr r3, [r7, #4]
80017f8: 699b ldr r3, [r3, #24]
80017fa: 2b01 cmp r3, #1
80017fc: d028 beq.n 8001850 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80017fe: 68fb ldr r3, [r7, #12]
8001800: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001804: 687b ldr r3, [r7, #4]
8001806: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001808: 429a cmp r2, r3
800180a: d121 bne.n 8001850 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
800180c: 68fb ldr r3, [r7, #12]
800180e: f003 023f and.w r2, r3, #63 ; 0x3f
8001812: 687b ldr r3, [r7, #4]
8001814: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001816: 429a cmp r2, r3
8001818: d11a bne.n 8001850 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
800181a: 68fa ldr r2, [r7, #12]
800181c: f647 73c0 movw r3, #32704 ; 0x7fc0
8001820: 4013 ands r3, r2
8001822: 687a ldr r2, [r7, #4]
8001824: 6a52 ldr r2, [r2, #36] ; 0x24
8001826: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001828: 4293 cmp r3, r2
800182a: d111 bne.n 8001850 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
800182c: 68fb ldr r3, [r7, #12]
800182e: f403 3240 and.w r2, r3, #196608 ; 0x30000
8001832: 687b ldr r3, [r7, #4]
8001834: 6a9b ldr r3, [r3, #40] ; 0x28
8001836: 085b lsrs r3, r3, #1
8001838: 3b01 subs r3, #1
800183a: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
800183c: 429a cmp r2, r3
800183e: d107 bne.n 8001850 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001840: 68fb ldr r3, [r7, #12]
8001842: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8001846: 687b ldr r3, [r7, #4]
8001848: 6adb ldr r3, [r3, #44] ; 0x2c
800184a: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
800184c: 429a cmp r2, r3
800184e: d001 beq.n 8001854 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
8001850: 2301 movs r3, #1
8001852: e000 b.n 8001856 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8001854: 2300 movs r3, #0
}
8001856: 4618 mov r0, r3
8001858: 3718 adds r7, #24
800185a: 46bd mov sp, r7
800185c: bd80 pop {r7, pc}
800185e: bf00 nop
8001860: 40023800 .word 0x40023800
08001864 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001864: b580 push {r7, lr}
8001866: b084 sub sp, #16
8001868: af00 add r7, sp, #0
800186a: 6078 str r0, [r7, #4]
800186c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800186e: 687b ldr r3, [r7, #4]
8001870: 2b00 cmp r3, #0
8001872: d101 bne.n 8001878 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001874: 2301 movs r3, #1
8001876: e0cc b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001878: 4b68 ldr r3, [pc, #416] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
800187a: 681b ldr r3, [r3, #0]
800187c: f003 0307 and.w r3, r3, #7
8001880: 683a ldr r2, [r7, #0]
8001882: 429a cmp r2, r3
8001884: d90c bls.n 80018a0 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001886: 4b65 ldr r3, [pc, #404] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
8001888: 683a ldr r2, [r7, #0]
800188a: b2d2 uxtb r2, r2
800188c: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800188e: 4b63 ldr r3, [pc, #396] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
8001890: 681b ldr r3, [r3, #0]
8001892: f003 0307 and.w r3, r3, #7
8001896: 683a ldr r2, [r7, #0]
8001898: 429a cmp r2, r3
800189a: d001 beq.n 80018a0 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
800189c: 2301 movs r3, #1
800189e: e0b8 b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80018a0: 687b ldr r3, [r7, #4]
80018a2: 681b ldr r3, [r3, #0]
80018a4: f003 0302 and.w r3, r3, #2
80018a8: 2b00 cmp r3, #0
80018aa: d020 beq.n 80018ee <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80018ac: 687b ldr r3, [r7, #4]
80018ae: 681b ldr r3, [r3, #0]
80018b0: f003 0304 and.w r3, r3, #4
80018b4: 2b00 cmp r3, #0
80018b6: d005 beq.n 80018c4 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80018b8: 4b59 ldr r3, [pc, #356] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018ba: 689b ldr r3, [r3, #8]
80018bc: 4a58 ldr r2, [pc, #352] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018be: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80018c2: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80018c4: 687b ldr r3, [r7, #4]
80018c6: 681b ldr r3, [r3, #0]
80018c8: f003 0308 and.w r3, r3, #8
80018cc: 2b00 cmp r3, #0
80018ce: d005 beq.n 80018dc <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80018d0: 4b53 ldr r3, [pc, #332] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018d2: 689b ldr r3, [r3, #8]
80018d4: 4a52 ldr r2, [pc, #328] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018d6: f443 4360 orr.w r3, r3, #57344 ; 0xe000
80018da: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80018dc: 4b50 ldr r3, [pc, #320] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018de: 689b ldr r3, [r3, #8]
80018e0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80018e4: 687b ldr r3, [r7, #4]
80018e6: 689b ldr r3, [r3, #8]
80018e8: 494d ldr r1, [pc, #308] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80018ea: 4313 orrs r3, r2
80018ec: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80018ee: 687b ldr r3, [r7, #4]
80018f0: 681b ldr r3, [r3, #0]
80018f2: f003 0301 and.w r3, r3, #1
80018f6: 2b00 cmp r3, #0
80018f8: d044 beq.n 8001984 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80018fa: 687b ldr r3, [r7, #4]
80018fc: 685b ldr r3, [r3, #4]
80018fe: 2b01 cmp r3, #1
8001900: d107 bne.n 8001912 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001902: 4b47 ldr r3, [pc, #284] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001904: 681b ldr r3, [r3, #0]
8001906: f403 3300 and.w r3, r3, #131072 ; 0x20000
800190a: 2b00 cmp r3, #0
800190c: d119 bne.n 8001942 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800190e: 2301 movs r3, #1
8001910: e07f b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001912: 687b ldr r3, [r7, #4]
8001914: 685b ldr r3, [r3, #4]
8001916: 2b02 cmp r3, #2
8001918: d003 beq.n 8001922 <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
800191a: 687b ldr r3, [r7, #4]
800191c: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800191e: 2b03 cmp r3, #3
8001920: d107 bne.n 8001932 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001922: 4b3f ldr r3, [pc, #252] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001924: 681b ldr r3, [r3, #0]
8001926: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800192a: 2b00 cmp r3, #0
800192c: d109 bne.n 8001942 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800192e: 2301 movs r3, #1
8001930: e06f b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001932: 4b3b ldr r3, [pc, #236] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001934: 681b ldr r3, [r3, #0]
8001936: f003 0302 and.w r3, r3, #2
800193a: 2b00 cmp r3, #0
800193c: d101 bne.n 8001942 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800193e: 2301 movs r3, #1
8001940: e067 b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001942: 4b37 ldr r3, [pc, #220] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001944: 689b ldr r3, [r3, #8]
8001946: f023 0203 bic.w r2, r3, #3
800194a: 687b ldr r3, [r7, #4]
800194c: 685b ldr r3, [r3, #4]
800194e: 4934 ldr r1, [pc, #208] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001950: 4313 orrs r3, r2
8001952: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001954: f7ff fa38 bl 8000dc8 <HAL_GetTick>
8001958: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800195a: e00a b.n 8001972 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800195c: f7ff fa34 bl 8000dc8 <HAL_GetTick>
8001960: 4602 mov r2, r0
8001962: 68fb ldr r3, [r7, #12]
8001964: 1ad3 subs r3, r2, r3
8001966: f241 3288 movw r2, #5000 ; 0x1388
800196a: 4293 cmp r3, r2
800196c: d901 bls.n 8001972 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800196e: 2303 movs r3, #3
8001970: e04f b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001972: 4b2b ldr r3, [pc, #172] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
8001974: 689b ldr r3, [r3, #8]
8001976: f003 020c and.w r2, r3, #12
800197a: 687b ldr r3, [r7, #4]
800197c: 685b ldr r3, [r3, #4]
800197e: 009b lsls r3, r3, #2
8001980: 429a cmp r2, r3
8001982: d1eb bne.n 800195c <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001984: 4b25 ldr r3, [pc, #148] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
8001986: 681b ldr r3, [r3, #0]
8001988: f003 0307 and.w r3, r3, #7
800198c: 683a ldr r2, [r7, #0]
800198e: 429a cmp r2, r3
8001990: d20c bcs.n 80019ac <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001992: 4b22 ldr r3, [pc, #136] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
8001994: 683a ldr r2, [r7, #0]
8001996: b2d2 uxtb r2, r2
8001998: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800199a: 4b20 ldr r3, [pc, #128] ; (8001a1c <HAL_RCC_ClockConfig+0x1b8>)
800199c: 681b ldr r3, [r3, #0]
800199e: f003 0307 and.w r3, r3, #7
80019a2: 683a ldr r2, [r7, #0]
80019a4: 429a cmp r2, r3
80019a6: d001 beq.n 80019ac <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80019a8: 2301 movs r3, #1
80019aa: e032 b.n 8001a12 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80019ac: 687b ldr r3, [r7, #4]
80019ae: 681b ldr r3, [r3, #0]
80019b0: f003 0304 and.w r3, r3, #4
80019b4: 2b00 cmp r3, #0
80019b6: d008 beq.n 80019ca <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80019b8: 4b19 ldr r3, [pc, #100] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80019ba: 689b ldr r3, [r3, #8]
80019bc: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80019c0: 687b ldr r3, [r7, #4]
80019c2: 68db ldr r3, [r3, #12]
80019c4: 4916 ldr r1, [pc, #88] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80019c6: 4313 orrs r3, r2
80019c8: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80019ca: 687b ldr r3, [r7, #4]
80019cc: 681b ldr r3, [r3, #0]
80019ce: f003 0308 and.w r3, r3, #8
80019d2: 2b00 cmp r3, #0
80019d4: d009 beq.n 80019ea <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80019d6: 4b12 ldr r3, [pc, #72] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80019d8: 689b ldr r3, [r3, #8]
80019da: f423 4260 bic.w r2, r3, #57344 ; 0xe000
80019de: 687b ldr r3, [r7, #4]
80019e0: 691b ldr r3, [r3, #16]
80019e2: 00db lsls r3, r3, #3
80019e4: 490e ldr r1, [pc, #56] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80019e6: 4313 orrs r3, r2
80019e8: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80019ea: f000 f821 bl 8001a30 <HAL_RCC_GetSysClockFreq>
80019ee: 4602 mov r2, r0
80019f0: 4b0b ldr r3, [pc, #44] ; (8001a20 <HAL_RCC_ClockConfig+0x1bc>)
80019f2: 689b ldr r3, [r3, #8]
80019f4: 091b lsrs r3, r3, #4
80019f6: f003 030f and.w r3, r3, #15
80019fa: 490a ldr r1, [pc, #40] ; (8001a24 <HAL_RCC_ClockConfig+0x1c0>)
80019fc: 5ccb ldrb r3, [r1, r3]
80019fe: fa22 f303 lsr.w r3, r2, r3
8001a02: 4a09 ldr r2, [pc, #36] ; (8001a28 <HAL_RCC_ClockConfig+0x1c4>)
8001a04: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001a06: 4b09 ldr r3, [pc, #36] ; (8001a2c <HAL_RCC_ClockConfig+0x1c8>)
8001a08: 681b ldr r3, [r3, #0]
8001a0a: 4618 mov r0, r3
8001a0c: f7ff f998 bl 8000d40 <HAL_InitTick>
return HAL_OK;
8001a10: 2300 movs r3, #0
}
8001a12: 4618 mov r0, r3
8001a14: 3710 adds r7, #16
8001a16: 46bd mov sp, r7
8001a18: bd80 pop {r7, pc}
8001a1a: bf00 nop
8001a1c: 40023c00 .word 0x40023c00
8001a20: 40023800 .word 0x40023800
8001a24: 08002c2c .word 0x08002c2c
8001a28: 20000000 .word 0x20000000
8001a2c: 20000004 .word 0x20000004
08001a30 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001a30: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001a34: b090 sub sp, #64 ; 0x40
8001a36: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001a38: 2300 movs r3, #0
8001a3a: 637b str r3, [r7, #52] ; 0x34
8001a3c: 2300 movs r3, #0
8001a3e: 63fb str r3, [r7, #60] ; 0x3c
8001a40: 2300 movs r3, #0
8001a42: 633b str r3, [r7, #48] ; 0x30
uint32_t sysclockfreq = 0U;
8001a44: 2300 movs r3, #0
8001a46: 63bb str r3, [r7, #56] ; 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001a48: 4b59 ldr r3, [pc, #356] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001a4a: 689b ldr r3, [r3, #8]
8001a4c: f003 030c and.w r3, r3, #12
8001a50: 2b08 cmp r3, #8
8001a52: d00d beq.n 8001a70 <HAL_RCC_GetSysClockFreq+0x40>
8001a54: 2b08 cmp r3, #8
8001a56: f200 80a1 bhi.w 8001b9c <HAL_RCC_GetSysClockFreq+0x16c>
8001a5a: 2b00 cmp r3, #0
8001a5c: d002 beq.n 8001a64 <HAL_RCC_GetSysClockFreq+0x34>
8001a5e: 2b04 cmp r3, #4
8001a60: d003 beq.n 8001a6a <HAL_RCC_GetSysClockFreq+0x3a>
8001a62: e09b b.n 8001b9c <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001a64: 4b53 ldr r3, [pc, #332] ; (8001bb4 <HAL_RCC_GetSysClockFreq+0x184>)
8001a66: 63bb str r3, [r7, #56] ; 0x38
break;
8001a68: e09b b.n 8001ba2 <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001a6a: 4b53 ldr r3, [pc, #332] ; (8001bb8 <HAL_RCC_GetSysClockFreq+0x188>)
8001a6c: 63bb str r3, [r7, #56] ; 0x38
break;
8001a6e: e098 b.n 8001ba2 <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8001a70: 4b4f ldr r3, [pc, #316] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001a72: 685b ldr r3, [r3, #4]
8001a74: f003 033f and.w r3, r3, #63 ; 0x3f
8001a78: 637b str r3, [r7, #52] ; 0x34
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001a7a: 4b4d ldr r3, [pc, #308] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001a7c: 685b ldr r3, [r3, #4]
8001a7e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001a82: 2b00 cmp r3, #0
8001a84: d028 beq.n 8001ad8 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001a86: 4b4a ldr r3, [pc, #296] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001a88: 685b ldr r3, [r3, #4]
8001a8a: 099b lsrs r3, r3, #6
8001a8c: 2200 movs r2, #0
8001a8e: 623b str r3, [r7, #32]
8001a90: 627a str r2, [r7, #36] ; 0x24
8001a92: 6a3b ldr r3, [r7, #32]
8001a94: f3c3 0008 ubfx r0, r3, #0, #9
8001a98: 2100 movs r1, #0
8001a9a: 4b47 ldr r3, [pc, #284] ; (8001bb8 <HAL_RCC_GetSysClockFreq+0x188>)
8001a9c: fb03 f201 mul.w r2, r3, r1
8001aa0: 2300 movs r3, #0
8001aa2: fb00 f303 mul.w r3, r0, r3
8001aa6: 4413 add r3, r2
8001aa8: 4a43 ldr r2, [pc, #268] ; (8001bb8 <HAL_RCC_GetSysClockFreq+0x188>)
8001aaa: fba0 1202 umull r1, r2, r0, r2
8001aae: 62fa str r2, [r7, #44] ; 0x2c
8001ab0: 460a mov r2, r1
8001ab2: 62ba str r2, [r7, #40] ; 0x28
8001ab4: 6afa ldr r2, [r7, #44] ; 0x2c
8001ab6: 4413 add r3, r2
8001ab8: 62fb str r3, [r7, #44] ; 0x2c
8001aba: 6b7b ldr r3, [r7, #52] ; 0x34
8001abc: 2200 movs r2, #0
8001abe: 61bb str r3, [r7, #24]
8001ac0: 61fa str r2, [r7, #28]
8001ac2: e9d7 2306 ldrd r2, r3, [r7, #24]
8001ac6: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28
8001aca: f7fe fb83 bl 80001d4 <__aeabi_uldivmod>
8001ace: 4602 mov r2, r0
8001ad0: 460b mov r3, r1
8001ad2: 4613 mov r3, r2
8001ad4: 63fb str r3, [r7, #60] ; 0x3c
8001ad6: e053 b.n 8001b80 <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001ad8: 4b35 ldr r3, [pc, #212] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001ada: 685b ldr r3, [r3, #4]
8001adc: 099b lsrs r3, r3, #6
8001ade: 2200 movs r2, #0
8001ae0: 613b str r3, [r7, #16]
8001ae2: 617a str r2, [r7, #20]
8001ae4: 693b ldr r3, [r7, #16]
8001ae6: f3c3 0a08 ubfx sl, r3, #0, #9
8001aea: f04f 0b00 mov.w fp, #0
8001aee: 4652 mov r2, sl
8001af0: 465b mov r3, fp
8001af2: f04f 0000 mov.w r0, #0
8001af6: f04f 0100 mov.w r1, #0
8001afa: 0159 lsls r1, r3, #5
8001afc: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001b00: 0150 lsls r0, r2, #5
8001b02: 4602 mov r2, r0
8001b04: 460b mov r3, r1
8001b06: ebb2 080a subs.w r8, r2, sl
8001b0a: eb63 090b sbc.w r9, r3, fp
8001b0e: f04f 0200 mov.w r2, #0
8001b12: f04f 0300 mov.w r3, #0
8001b16: ea4f 1389 mov.w r3, r9, lsl #6
8001b1a: ea43 6398 orr.w r3, r3, r8, lsr #26
8001b1e: ea4f 1288 mov.w r2, r8, lsl #6
8001b22: ebb2 0408 subs.w r4, r2, r8
8001b26: eb63 0509 sbc.w r5, r3, r9
8001b2a: f04f 0200 mov.w r2, #0
8001b2e: f04f 0300 mov.w r3, #0
8001b32: 00eb lsls r3, r5, #3
8001b34: ea43 7354 orr.w r3, r3, r4, lsr #29
8001b38: 00e2 lsls r2, r4, #3
8001b3a: 4614 mov r4, r2
8001b3c: 461d mov r5, r3
8001b3e: eb14 030a adds.w r3, r4, sl
8001b42: 603b str r3, [r7, #0]
8001b44: eb45 030b adc.w r3, r5, fp
8001b48: 607b str r3, [r7, #4]
8001b4a: f04f 0200 mov.w r2, #0
8001b4e: f04f 0300 mov.w r3, #0
8001b52: e9d7 4500 ldrd r4, r5, [r7]
8001b56: 4629 mov r1, r5
8001b58: 028b lsls r3, r1, #10
8001b5a: 4621 mov r1, r4
8001b5c: ea43 5391 orr.w r3, r3, r1, lsr #22
8001b60: 4621 mov r1, r4
8001b62: 028a lsls r2, r1, #10
8001b64: 4610 mov r0, r2
8001b66: 4619 mov r1, r3
8001b68: 6b7b ldr r3, [r7, #52] ; 0x34
8001b6a: 2200 movs r2, #0
8001b6c: 60bb str r3, [r7, #8]
8001b6e: 60fa str r2, [r7, #12]
8001b70: e9d7 2302 ldrd r2, r3, [r7, #8]
8001b74: f7fe fb2e bl 80001d4 <__aeabi_uldivmod>
8001b78: 4602 mov r2, r0
8001b7a: 460b mov r3, r1
8001b7c: 4613 mov r3, r2
8001b7e: 63fb str r3, [r7, #60] ; 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001b80: 4b0b ldr r3, [pc, #44] ; (8001bb0 <HAL_RCC_GetSysClockFreq+0x180>)
8001b82: 685b ldr r3, [r3, #4]
8001b84: 0c1b lsrs r3, r3, #16
8001b86: f003 0303 and.w r3, r3, #3
8001b8a: 3301 adds r3, #1
8001b8c: 005b lsls r3, r3, #1
8001b8e: 633b str r3, [r7, #48] ; 0x30
sysclockfreq = pllvco/pllp;
8001b90: 6bfa ldr r2, [r7, #60] ; 0x3c
8001b92: 6b3b ldr r3, [r7, #48] ; 0x30
8001b94: fbb2 f3f3 udiv r3, r2, r3
8001b98: 63bb str r3, [r7, #56] ; 0x38
break;
8001b9a: e002 b.n 8001ba2 <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
8001b9c: 4b05 ldr r3, [pc, #20] ; (8001bb4 <HAL_RCC_GetSysClockFreq+0x184>)
8001b9e: 63bb str r3, [r7, #56] ; 0x38
break;
8001ba0: bf00 nop
}
}
return sysclockfreq;
8001ba2: 6bbb ldr r3, [r7, #56] ; 0x38
}
8001ba4: 4618 mov r0, r3
8001ba6: 3740 adds r7, #64 ; 0x40
8001ba8: 46bd mov sp, r7
8001baa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001bae: bf00 nop
8001bb0: 40023800 .word 0x40023800
8001bb4: 00f42400 .word 0x00f42400
8001bb8: 017d7840 .word 0x017d7840
08001bbc <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001bbc: b580 push {r7, lr}
8001bbe: b082 sub sp, #8
8001bc0: af00 add r7, sp, #0
8001bc2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 2b00 cmp r3, #0
8001bc8: d101 bne.n 8001bce <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001bca: 2301 movs r3, #1
8001bcc: e041 b.n 8001c52 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001bce: 687b ldr r3, [r7, #4]
8001bd0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001bd4: b2db uxtb r3, r3
8001bd6: 2b00 cmp r3, #0
8001bd8: d106 bne.n 8001be8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001bda: 687b ldr r3, [r7, #4]
8001bdc: 2200 movs r2, #0
8001bde: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8001be2: 6878 ldr r0, [r7, #4]
8001be4: f7fe ff84 bl 8000af0 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001be8: 687b ldr r3, [r7, #4]
8001bea: 2202 movs r2, #2
8001bec: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: 681a ldr r2, [r3, #0]
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 3304 adds r3, #4
8001bf8: 4619 mov r1, r3
8001bfa: 4610 mov r0, r2
8001bfc: f000 fc58 bl 80024b0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001c00: 687b ldr r3, [r7, #4]
8001c02: 2201 movs r2, #1
8001c04: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001c08: 687b ldr r3, [r7, #4]
8001c0a: 2201 movs r2, #1
8001c0c: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001c10: 687b ldr r3, [r7, #4]
8001c12: 2201 movs r2, #1
8001c14: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001c18: 687b ldr r3, [r7, #4]
8001c1a: 2201 movs r2, #1
8001c1c: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001c20: 687b ldr r3, [r7, #4]
8001c22: 2201 movs r2, #1
8001c24: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001c28: 687b ldr r3, [r7, #4]
8001c2a: 2201 movs r2, #1
8001c2c: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001c30: 687b ldr r3, [r7, #4]
8001c32: 2201 movs r2, #1
8001c34: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001c38: 687b ldr r3, [r7, #4]
8001c3a: 2201 movs r2, #1
8001c3c: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001c40: 687b ldr r3, [r7, #4]
8001c42: 2201 movs r2, #1
8001c44: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001c48: 687b ldr r3, [r7, #4]
8001c4a: 2201 movs r2, #1
8001c4c: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001c50: 2300 movs r3, #0
}
8001c52: 4618 mov r0, r3
8001c54: 3708 adds r7, #8
8001c56: 46bd mov sp, r7
8001c58: bd80 pop {r7, pc}
...
08001c5c <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8001c5c: b480 push {r7}
8001c5e: b085 sub sp, #20
8001c60: af00 add r7, sp, #0
8001c62: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8001c64: 687b ldr r3, [r7, #4]
8001c66: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001c6a: b2db uxtb r3, r3
8001c6c: 2b01 cmp r3, #1
8001c6e: d001 beq.n 8001c74 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8001c70: 2301 movs r3, #1
8001c72: e044 b.n 8001cfe <HAL_TIM_Base_Start_IT+0xa2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001c74: 687b ldr r3, [r7, #4]
8001c76: 2202 movs r2, #2
8001c78: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 681b ldr r3, [r3, #0]
8001c80: 68da ldr r2, [r3, #12]
8001c82: 687b ldr r3, [r7, #4]
8001c84: 681b ldr r3, [r3, #0]
8001c86: f042 0201 orr.w r2, r2, #1
8001c8a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001c8c: 687b ldr r3, [r7, #4]
8001c8e: 681b ldr r3, [r3, #0]
8001c90: 4a1e ldr r2, [pc, #120] ; (8001d0c <HAL_TIM_Base_Start_IT+0xb0>)
8001c92: 4293 cmp r3, r2
8001c94: d018 beq.n 8001cc8 <HAL_TIM_Base_Start_IT+0x6c>
8001c96: 687b ldr r3, [r7, #4]
8001c98: 681b ldr r3, [r3, #0]
8001c9a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001c9e: d013 beq.n 8001cc8 <HAL_TIM_Base_Start_IT+0x6c>
8001ca0: 687b ldr r3, [r7, #4]
8001ca2: 681b ldr r3, [r3, #0]
8001ca4: 4a1a ldr r2, [pc, #104] ; (8001d10 <HAL_TIM_Base_Start_IT+0xb4>)
8001ca6: 4293 cmp r3, r2
8001ca8: d00e beq.n 8001cc8 <HAL_TIM_Base_Start_IT+0x6c>
8001caa: 687b ldr r3, [r7, #4]
8001cac: 681b ldr r3, [r3, #0]
8001cae: 4a19 ldr r2, [pc, #100] ; (8001d14 <HAL_TIM_Base_Start_IT+0xb8>)
8001cb0: 4293 cmp r3, r2
8001cb2: d009 beq.n 8001cc8 <HAL_TIM_Base_Start_IT+0x6c>
8001cb4: 687b ldr r3, [r7, #4]
8001cb6: 681b ldr r3, [r3, #0]
8001cb8: 4a17 ldr r2, [pc, #92] ; (8001d18 <HAL_TIM_Base_Start_IT+0xbc>)
8001cba: 4293 cmp r3, r2
8001cbc: d004 beq.n 8001cc8 <HAL_TIM_Base_Start_IT+0x6c>
8001cbe: 687b ldr r3, [r7, #4]
8001cc0: 681b ldr r3, [r3, #0]
8001cc2: 4a16 ldr r2, [pc, #88] ; (8001d1c <HAL_TIM_Base_Start_IT+0xc0>)
8001cc4: 4293 cmp r3, r2
8001cc6: d111 bne.n 8001cec <HAL_TIM_Base_Start_IT+0x90>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8001cc8: 687b ldr r3, [r7, #4]
8001cca: 681b ldr r3, [r3, #0]
8001ccc: 689b ldr r3, [r3, #8]
8001cce: f003 0307 and.w r3, r3, #7
8001cd2: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001cd4: 68fb ldr r3, [r7, #12]
8001cd6: 2b06 cmp r3, #6
8001cd8: d010 beq.n 8001cfc <HAL_TIM_Base_Start_IT+0xa0>
{
__HAL_TIM_ENABLE(htim);
8001cda: 687b ldr r3, [r7, #4]
8001cdc: 681b ldr r3, [r3, #0]
8001cde: 681a ldr r2, [r3, #0]
8001ce0: 687b ldr r3, [r7, #4]
8001ce2: 681b ldr r3, [r3, #0]
8001ce4: f042 0201 orr.w r2, r2, #1
8001ce8: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001cea: e007 b.n 8001cfc <HAL_TIM_Base_Start_IT+0xa0>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8001cec: 687b ldr r3, [r7, #4]
8001cee: 681b ldr r3, [r3, #0]
8001cf0: 681a ldr r2, [r3, #0]
8001cf2: 687b ldr r3, [r7, #4]
8001cf4: 681b ldr r3, [r3, #0]
8001cf6: f042 0201 orr.w r2, r2, #1
8001cfa: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8001cfc: 2300 movs r3, #0
}
8001cfe: 4618 mov r0, r3
8001d00: 3714 adds r7, #20
8001d02: 46bd mov sp, r7
8001d04: f85d 7b04 ldr.w r7, [sp], #4
8001d08: 4770 bx lr
8001d0a: bf00 nop
8001d0c: 40010000 .word 0x40010000
8001d10: 40000400 .word 0x40000400
8001d14: 40000800 .word 0x40000800
8001d18: 40000c00 .word 0x40000c00
8001d1c: 40014000 .word 0x40014000
08001d20 <HAL_TIM_OC_Init>:
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
8001d20: b580 push {r7, lr}
8001d22: b082 sub sp, #8
8001d24: af00 add r7, sp, #0
8001d26: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001d28: 687b ldr r3, [r7, #4]
8001d2a: 2b00 cmp r3, #0
8001d2c: d101 bne.n 8001d32 <HAL_TIM_OC_Init+0x12>
{
return HAL_ERROR;
8001d2e: 2301 movs r3, #1
8001d30: e041 b.n 8001db6 <HAL_TIM_OC_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001d32: 687b ldr r3, [r7, #4]
8001d34: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001d38: b2db uxtb r3, r3
8001d3a: 2b00 cmp r3, #0
8001d3c: d106 bne.n 8001d4c <HAL_TIM_OC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 2200 movs r2, #0
8001d42: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OC_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
8001d46: 6878 ldr r0, [r7, #4]
8001d48: f000 f839 bl 8001dbe <HAL_TIM_OC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001d4c: 687b ldr r3, [r7, #4]
8001d4e: 2202 movs r2, #2
8001d50: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001d54: 687b ldr r3, [r7, #4]
8001d56: 681a ldr r2, [r3, #0]
8001d58: 687b ldr r3, [r7, #4]
8001d5a: 3304 adds r3, #4
8001d5c: 4619 mov r1, r3
8001d5e: 4610 mov r0, r2
8001d60: f000 fba6 bl 80024b0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001d64: 687b ldr r3, [r7, #4]
8001d66: 2201 movs r2, #1
8001d68: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001d6c: 687b ldr r3, [r7, #4]
8001d6e: 2201 movs r2, #1
8001d70: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001d74: 687b ldr r3, [r7, #4]
8001d76: 2201 movs r2, #1
8001d78: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001d7c: 687b ldr r3, [r7, #4]
8001d7e: 2201 movs r2, #1
8001d80: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001d84: 687b ldr r3, [r7, #4]
8001d86: 2201 movs r2, #1
8001d88: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001d8c: 687b ldr r3, [r7, #4]
8001d8e: 2201 movs r2, #1
8001d90: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001d94: 687b ldr r3, [r7, #4]
8001d96: 2201 movs r2, #1
8001d98: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001d9c: 687b ldr r3, [r7, #4]
8001d9e: 2201 movs r2, #1
8001da0: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001da4: 687b ldr r3, [r7, #4]
8001da6: 2201 movs r2, #1
8001da8: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001dac: 687b ldr r3, [r7, #4]
8001dae: 2201 movs r2, #1
8001db0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001db4: 2300 movs r3, #0
}
8001db6: 4618 mov r0, r3
8001db8: 3708 adds r7, #8
8001dba: 46bd mov sp, r7
8001dbc: bd80 pop {r7, pc}
08001dbe <HAL_TIM_OC_MspInit>:
* @brief Initializes the TIM Output Compare MSP.
* @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
8001dbe: b480 push {r7}
8001dc0: b083 sub sp, #12
8001dc2: af00 add r7, sp, #0
8001dc4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
8001dc6: bf00 nop
8001dc8: 370c adds r7, #12
8001dca: 46bd mov sp, r7
8001dcc: f85d 7b04 ldr.w r7, [sp], #4
8001dd0: 4770 bx lr
08001dd2 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8001dd2: b580 push {r7, lr}
8001dd4: b082 sub sp, #8
8001dd6: af00 add r7, sp, #0
8001dd8: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 2b00 cmp r3, #0
8001dde: d101 bne.n 8001de4 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8001de0: 2301 movs r3, #1
8001de2: e041 b.n 8001e68 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001de4: 687b ldr r3, [r7, #4]
8001de6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001dea: b2db uxtb r3, r3
8001dec: 2b00 cmp r3, #0
8001dee: d106 bne.n 8001dfe <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001df0: 687b ldr r3, [r7, #4]
8001df2: 2200 movs r2, #0
8001df4: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8001df8: 6878 ldr r0, [r7, #4]
8001dfa: f000 f839 bl 8001e70 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001dfe: 687b ldr r3, [r7, #4]
8001e00: 2202 movs r2, #2
8001e02: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001e06: 687b ldr r3, [r7, #4]
8001e08: 681a ldr r2, [r3, #0]
8001e0a: 687b ldr r3, [r7, #4]
8001e0c: 3304 adds r3, #4
8001e0e: 4619 mov r1, r3
8001e10: 4610 mov r0, r2
8001e12: f000 fb4d bl 80024b0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001e16: 687b ldr r3, [r7, #4]
8001e18: 2201 movs r2, #1
8001e1a: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001e1e: 687b ldr r3, [r7, #4]
8001e20: 2201 movs r2, #1
8001e22: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001e26: 687b ldr r3, [r7, #4]
8001e28: 2201 movs r2, #1
8001e2a: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 2201 movs r2, #1
8001e32: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001e36: 687b ldr r3, [r7, #4]
8001e38: 2201 movs r2, #1
8001e3a: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001e3e: 687b ldr r3, [r7, #4]
8001e40: 2201 movs r2, #1
8001e42: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001e46: 687b ldr r3, [r7, #4]
8001e48: 2201 movs r2, #1
8001e4a: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001e4e: 687b ldr r3, [r7, #4]
8001e50: 2201 movs r2, #1
8001e52: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001e56: 687b ldr r3, [r7, #4]
8001e58: 2201 movs r2, #1
8001e5a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001e5e: 687b ldr r3, [r7, #4]
8001e60: 2201 movs r2, #1
8001e62: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001e66: 2300 movs r3, #0
}
8001e68: 4618 mov r0, r3
8001e6a: 3708 adds r7, #8
8001e6c: 46bd mov sp, r7
8001e6e: bd80 pop {r7, pc}
08001e70 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8001e70: b480 push {r7}
8001e72: b083 sub sp, #12
8001e74: af00 add r7, sp, #0
8001e76: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8001e78: bf00 nop
8001e7a: 370c adds r7, #12
8001e7c: 46bd mov sp, r7
8001e7e: f85d 7b04 ldr.w r7, [sp], #4
8001e82: 4770 bx lr
08001e84 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8001e84: b580 push {r7, lr}
8001e86: b082 sub sp, #8
8001e88: af00 add r7, sp, #0
8001e8a: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8001e8c: 687b ldr r3, [r7, #4]
8001e8e: 681b ldr r3, [r3, #0]
8001e90: 691b ldr r3, [r3, #16]
8001e92: f003 0302 and.w r3, r3, #2
8001e96: 2b02 cmp r3, #2
8001e98: d122 bne.n 8001ee0 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 681b ldr r3, [r3, #0]
8001e9e: 68db ldr r3, [r3, #12]
8001ea0: f003 0302 and.w r3, r3, #2
8001ea4: 2b02 cmp r3, #2
8001ea6: d11b bne.n 8001ee0 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 681b ldr r3, [r3, #0]
8001eac: f06f 0202 mvn.w r2, #2
8001eb0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 2201 movs r2, #1
8001eb6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8001eb8: 687b ldr r3, [r7, #4]
8001eba: 681b ldr r3, [r3, #0]
8001ebc: 699b ldr r3, [r3, #24]
8001ebe: f003 0303 and.w r3, r3, #3
8001ec2: 2b00 cmp r3, #0
8001ec4: d003 beq.n 8001ece <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001ec6: 6878 ldr r0, [r7, #4]
8001ec8: f000 fad3 bl 8002472 <HAL_TIM_IC_CaptureCallback>
8001ecc: e005 b.n 8001eda <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001ece: 6878 ldr r0, [r7, #4]
8001ed0: f000 fac5 bl 800245e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001ed4: 6878 ldr r0, [r7, #4]
8001ed6: f000 fad6 bl 8002486 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001eda: 687b ldr r3, [r7, #4]
8001edc: 2200 movs r2, #0
8001ede: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8001ee0: 687b ldr r3, [r7, #4]
8001ee2: 681b ldr r3, [r3, #0]
8001ee4: 691b ldr r3, [r3, #16]
8001ee6: f003 0304 and.w r3, r3, #4
8001eea: 2b04 cmp r3, #4
8001eec: d122 bne.n 8001f34 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8001eee: 687b ldr r3, [r7, #4]
8001ef0: 681b ldr r3, [r3, #0]
8001ef2: 68db ldr r3, [r3, #12]
8001ef4: f003 0304 and.w r3, r3, #4
8001ef8: 2b04 cmp r3, #4
8001efa: d11b bne.n 8001f34 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8001efc: 687b ldr r3, [r7, #4]
8001efe: 681b ldr r3, [r3, #0]
8001f00: f06f 0204 mvn.w r2, #4
8001f04: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8001f06: 687b ldr r3, [r7, #4]
8001f08: 2202 movs r2, #2
8001f0a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8001f0c: 687b ldr r3, [r7, #4]
8001f0e: 681b ldr r3, [r3, #0]
8001f10: 699b ldr r3, [r3, #24]
8001f12: f403 7340 and.w r3, r3, #768 ; 0x300
8001f16: 2b00 cmp r3, #0
8001f18: d003 beq.n 8001f22 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001f1a: 6878 ldr r0, [r7, #4]
8001f1c: f000 faa9 bl 8002472 <HAL_TIM_IC_CaptureCallback>
8001f20: e005 b.n 8001f2e <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001f22: 6878 ldr r0, [r7, #4]
8001f24: f000 fa9b bl 800245e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001f28: 6878 ldr r0, [r7, #4]
8001f2a: f000 faac bl 8002486 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001f2e: 687b ldr r3, [r7, #4]
8001f30: 2200 movs r2, #0
8001f32: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8001f34: 687b ldr r3, [r7, #4]
8001f36: 681b ldr r3, [r3, #0]
8001f38: 691b ldr r3, [r3, #16]
8001f3a: f003 0308 and.w r3, r3, #8
8001f3e: 2b08 cmp r3, #8
8001f40: d122 bne.n 8001f88 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8001f42: 687b ldr r3, [r7, #4]
8001f44: 681b ldr r3, [r3, #0]
8001f46: 68db ldr r3, [r3, #12]
8001f48: f003 0308 and.w r3, r3, #8
8001f4c: 2b08 cmp r3, #8
8001f4e: d11b bne.n 8001f88 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8001f50: 687b ldr r3, [r7, #4]
8001f52: 681b ldr r3, [r3, #0]
8001f54: f06f 0208 mvn.w r2, #8
8001f58: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 2204 movs r2, #4
8001f5e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8001f60: 687b ldr r3, [r7, #4]
8001f62: 681b ldr r3, [r3, #0]
8001f64: 69db ldr r3, [r3, #28]
8001f66: f003 0303 and.w r3, r3, #3
8001f6a: 2b00 cmp r3, #0
8001f6c: d003 beq.n 8001f76 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001f6e: 6878 ldr r0, [r7, #4]
8001f70: f000 fa7f bl 8002472 <HAL_TIM_IC_CaptureCallback>
8001f74: e005 b.n 8001f82 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001f76: 6878 ldr r0, [r7, #4]
8001f78: f000 fa71 bl 800245e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001f7c: 6878 ldr r0, [r7, #4]
8001f7e: f000 fa82 bl 8002486 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001f82: 687b ldr r3, [r7, #4]
8001f84: 2200 movs r2, #0
8001f86: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 681b ldr r3, [r3, #0]
8001f8c: 691b ldr r3, [r3, #16]
8001f8e: f003 0310 and.w r3, r3, #16
8001f92: 2b10 cmp r3, #16
8001f94: d122 bne.n 8001fdc <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8001f96: 687b ldr r3, [r7, #4]
8001f98: 681b ldr r3, [r3, #0]
8001f9a: 68db ldr r3, [r3, #12]
8001f9c: f003 0310 and.w r3, r3, #16
8001fa0: 2b10 cmp r3, #16
8001fa2: d11b bne.n 8001fdc <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 681b ldr r3, [r3, #0]
8001fa8: f06f 0210 mvn.w r2, #16
8001fac: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8001fae: 687b ldr r3, [r7, #4]
8001fb0: 2208 movs r2, #8
8001fb2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8001fb4: 687b ldr r3, [r7, #4]
8001fb6: 681b ldr r3, [r3, #0]
8001fb8: 69db ldr r3, [r3, #28]
8001fba: f403 7340 and.w r3, r3, #768 ; 0x300
8001fbe: 2b00 cmp r3, #0
8001fc0: d003 beq.n 8001fca <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001fc2: 6878 ldr r0, [r7, #4]
8001fc4: f000 fa55 bl 8002472 <HAL_TIM_IC_CaptureCallback>
8001fc8: e005 b.n 8001fd6 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001fca: 6878 ldr r0, [r7, #4]
8001fcc: f000 fa47 bl 800245e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001fd0: 6878 ldr r0, [r7, #4]
8001fd2: f000 fa58 bl 8002486 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001fd6: 687b ldr r3, [r7, #4]
8001fd8: 2200 movs r2, #0
8001fda: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8001fdc: 687b ldr r3, [r7, #4]
8001fde: 681b ldr r3, [r3, #0]
8001fe0: 691b ldr r3, [r3, #16]
8001fe2: f003 0301 and.w r3, r3, #1
8001fe6: 2b01 cmp r3, #1
8001fe8: d10e bne.n 8002008 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8001fea: 687b ldr r3, [r7, #4]
8001fec: 681b ldr r3, [r3, #0]
8001fee: 68db ldr r3, [r3, #12]
8001ff0: f003 0301 and.w r3, r3, #1
8001ff4: 2b01 cmp r3, #1
8001ff6: d107 bne.n 8002008 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8001ff8: 687b ldr r3, [r7, #4]
8001ffa: 681b ldr r3, [r3, #0]
8001ffc: f06f 0201 mvn.w r2, #1
8002000: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002002: 6878 ldr r0, [r7, #4]
8002004: f7fe fd2e bl 8000a64 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8002008: 687b ldr r3, [r7, #4]
800200a: 681b ldr r3, [r3, #0]
800200c: 691b ldr r3, [r3, #16]
800200e: f003 0380 and.w r3, r3, #128 ; 0x80
8002012: 2b80 cmp r3, #128 ; 0x80
8002014: d10e bne.n 8002034 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8002016: 687b ldr r3, [r7, #4]
8002018: 681b ldr r3, [r3, #0]
800201a: 68db ldr r3, [r3, #12]
800201c: f003 0380 and.w r3, r3, #128 ; 0x80
8002020: 2b80 cmp r3, #128 ; 0x80
8002022: d107 bne.n 8002034 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8002024: 687b ldr r3, [r7, #4]
8002026: 681b ldr r3, [r3, #0]
8002028: f06f 0280 mvn.w r2, #128 ; 0x80
800202c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
800202e: 6878 ldr r0, [r7, #4]
8002030: f000 fdae bl 8002b90 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8002034: 687b ldr r3, [r7, #4]
8002036: 681b ldr r3, [r3, #0]
8002038: 691b ldr r3, [r3, #16]
800203a: f003 0340 and.w r3, r3, #64 ; 0x40
800203e: 2b40 cmp r3, #64 ; 0x40
8002040: d10e bne.n 8002060 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8002042: 687b ldr r3, [r7, #4]
8002044: 681b ldr r3, [r3, #0]
8002046: 68db ldr r3, [r3, #12]
8002048: f003 0340 and.w r3, r3, #64 ; 0x40
800204c: 2b40 cmp r3, #64 ; 0x40
800204e: d107 bne.n 8002060 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8002050: 687b ldr r3, [r7, #4]
8002052: 681b ldr r3, [r3, #0]
8002054: f06f 0240 mvn.w r2, #64 ; 0x40
8002058: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
800205a: 6878 ldr r0, [r7, #4]
800205c: f000 fa1d bl 800249a <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8002060: 687b ldr r3, [r7, #4]
8002062: 681b ldr r3, [r3, #0]
8002064: 691b ldr r3, [r3, #16]
8002066: f003 0320 and.w r3, r3, #32
800206a: 2b20 cmp r3, #32
800206c: d10e bne.n 800208c <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
800206e: 687b ldr r3, [r7, #4]
8002070: 681b ldr r3, [r3, #0]
8002072: 68db ldr r3, [r3, #12]
8002074: f003 0320 and.w r3, r3, #32
8002078: 2b20 cmp r3, #32
800207a: d107 bne.n 800208c <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
800207c: 687b ldr r3, [r7, #4]
800207e: 681b ldr r3, [r3, #0]
8002080: f06f 0220 mvn.w r2, #32
8002084: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002086: 6878 ldr r0, [r7, #4]
8002088: f000 fd78 bl 8002b7c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
800208c: bf00 nop
800208e: 3708 adds r7, #8
8002090: 46bd mov sp, r7
8002092: bd80 pop {r7, pc}
08002094 <HAL_TIM_OC_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002094: b580 push {r7, lr}
8002096: b086 sub sp, #24
8002098: af00 add r7, sp, #0
800209a: 60f8 str r0, [r7, #12]
800209c: 60b9 str r1, [r7, #8]
800209e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80020a0: 2300 movs r3, #0
80020a2: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
/* Process Locked */
__HAL_LOCK(htim);
80020a4: 68fb ldr r3, [r7, #12]
80020a6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80020aa: 2b01 cmp r3, #1
80020ac: d101 bne.n 80020b2 <HAL_TIM_OC_ConfigChannel+0x1e>
80020ae: 2302 movs r3, #2
80020b0: e048 b.n 8002144 <HAL_TIM_OC_ConfigChannel+0xb0>
80020b2: 68fb ldr r3, [r7, #12]
80020b4: 2201 movs r2, #1
80020b6: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
80020ba: 687b ldr r3, [r7, #4]
80020bc: 2b0c cmp r3, #12
80020be: d839 bhi.n 8002134 <HAL_TIM_OC_ConfigChannel+0xa0>
80020c0: a201 add r2, pc, #4 ; (adr r2, 80020c8 <HAL_TIM_OC_ConfigChannel+0x34>)
80020c2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80020c6: bf00 nop
80020c8: 080020fd .word 0x080020fd
80020cc: 08002135 .word 0x08002135
80020d0: 08002135 .word 0x08002135
80020d4: 08002135 .word 0x08002135
80020d8: 0800210b .word 0x0800210b
80020dc: 08002135 .word 0x08002135
80020e0: 08002135 .word 0x08002135
80020e4: 08002135 .word 0x08002135
80020e8: 08002119 .word 0x08002119
80020ec: 08002135 .word 0x08002135
80020f0: 08002135 .word 0x08002135
80020f4: 08002135 .word 0x08002135
80020f8: 08002127 .word 0x08002127
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80020fc: 68fb ldr r3, [r7, #12]
80020fe: 681b ldr r3, [r3, #0]
8002100: 68b9 ldr r1, [r7, #8]
8002102: 4618 mov r0, r3
8002104: f000 fa54 bl 80025b0 <TIM_OC1_SetConfig>
break;
8002108: e017 b.n 800213a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
800210a: 68fb ldr r3, [r7, #12]
800210c: 681b ldr r3, [r3, #0]
800210e: 68b9 ldr r1, [r7, #8]
8002110: 4618 mov r0, r3
8002112: f000 fab3 bl 800267c <TIM_OC2_SetConfig>
break;
8002116: e010 b.n 800213a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002118: 68fb ldr r3, [r7, #12]
800211a: 681b ldr r3, [r3, #0]
800211c: 68b9 ldr r1, [r7, #8]
800211e: 4618 mov r0, r3
8002120: f000 fb18 bl 8002754 <TIM_OC3_SetConfig>
break;
8002124: e009 b.n 800213a <HAL_TIM_OC_ConfigChannel+0xa6>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002126: 68fb ldr r3, [r7, #12]
8002128: 681b ldr r3, [r3, #0]
800212a: 68b9 ldr r1, [r7, #8]
800212c: 4618 mov r0, r3
800212e: f000 fb7b bl 8002828 <TIM_OC4_SetConfig>
break;
8002132: e002 b.n 800213a <HAL_TIM_OC_ConfigChannel+0xa6>
}
default:
status = HAL_ERROR;
8002134: 2301 movs r3, #1
8002136: 75fb strb r3, [r7, #23]
break;
8002138: bf00 nop
}
__HAL_UNLOCK(htim);
800213a: 68fb ldr r3, [r7, #12]
800213c: 2200 movs r2, #0
800213e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8002142: 7dfb ldrb r3, [r7, #23]
}
8002144: 4618 mov r0, r3
8002146: 3718 adds r7, #24
8002148: 46bd mov sp, r7
800214a: bd80 pop {r7, pc}
0800214c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
800214c: b580 push {r7, lr}
800214e: b086 sub sp, #24
8002150: af00 add r7, sp, #0
8002152: 60f8 str r0, [r7, #12]
8002154: 60b9 str r1, [r7, #8]
8002156: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002158: 2300 movs r3, #0
800215a: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
800215c: 68fb ldr r3, [r7, #12]
800215e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002162: 2b01 cmp r3, #1
8002164: d101 bne.n 800216a <HAL_TIM_PWM_ConfigChannel+0x1e>
8002166: 2302 movs r3, #2
8002168: e0ae b.n 80022c8 <HAL_TIM_PWM_ConfigChannel+0x17c>
800216a: 68fb ldr r3, [r7, #12]
800216c: 2201 movs r2, #1
800216e: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8002172: 687b ldr r3, [r7, #4]
8002174: 2b0c cmp r3, #12
8002176: f200 809f bhi.w 80022b8 <HAL_TIM_PWM_ConfigChannel+0x16c>
800217a: a201 add r2, pc, #4 ; (adr r2, 8002180 <HAL_TIM_PWM_ConfigChannel+0x34>)
800217c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002180: 080021b5 .word 0x080021b5
8002184: 080022b9 .word 0x080022b9
8002188: 080022b9 .word 0x080022b9
800218c: 080022b9 .word 0x080022b9
8002190: 080021f5 .word 0x080021f5
8002194: 080022b9 .word 0x080022b9
8002198: 080022b9 .word 0x080022b9
800219c: 080022b9 .word 0x080022b9
80021a0: 08002237 .word 0x08002237
80021a4: 080022b9 .word 0x080022b9
80021a8: 080022b9 .word 0x080022b9
80021ac: 080022b9 .word 0x080022b9
80021b0: 08002277 .word 0x08002277
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80021b4: 68fb ldr r3, [r7, #12]
80021b6: 681b ldr r3, [r3, #0]
80021b8: 68b9 ldr r1, [r7, #8]
80021ba: 4618 mov r0, r3
80021bc: f000 f9f8 bl 80025b0 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
80021c0: 68fb ldr r3, [r7, #12]
80021c2: 681b ldr r3, [r3, #0]
80021c4: 699a ldr r2, [r3, #24]
80021c6: 68fb ldr r3, [r7, #12]
80021c8: 681b ldr r3, [r3, #0]
80021ca: f042 0208 orr.w r2, r2, #8
80021ce: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80021d0: 68fb ldr r3, [r7, #12]
80021d2: 681b ldr r3, [r3, #0]
80021d4: 699a ldr r2, [r3, #24]
80021d6: 68fb ldr r3, [r7, #12]
80021d8: 681b ldr r3, [r3, #0]
80021da: f022 0204 bic.w r2, r2, #4
80021de: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80021e0: 68fb ldr r3, [r7, #12]
80021e2: 681b ldr r3, [r3, #0]
80021e4: 6999 ldr r1, [r3, #24]
80021e6: 68bb ldr r3, [r7, #8]
80021e8: 691a ldr r2, [r3, #16]
80021ea: 68fb ldr r3, [r7, #12]
80021ec: 681b ldr r3, [r3, #0]
80021ee: 430a orrs r2, r1
80021f0: 619a str r2, [r3, #24]
break;
80021f2: e064 b.n 80022be <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80021f4: 68fb ldr r3, [r7, #12]
80021f6: 681b ldr r3, [r3, #0]
80021f8: 68b9 ldr r1, [r7, #8]
80021fa: 4618 mov r0, r3
80021fc: f000 fa3e bl 800267c <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8002200: 68fb ldr r3, [r7, #12]
8002202: 681b ldr r3, [r3, #0]
8002204: 699a ldr r2, [r3, #24]
8002206: 68fb ldr r3, [r7, #12]
8002208: 681b ldr r3, [r3, #0]
800220a: f442 6200 orr.w r2, r2, #2048 ; 0x800
800220e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8002210: 68fb ldr r3, [r7, #12]
8002212: 681b ldr r3, [r3, #0]
8002214: 699a ldr r2, [r3, #24]
8002216: 68fb ldr r3, [r7, #12]
8002218: 681b ldr r3, [r3, #0]
800221a: f422 6280 bic.w r2, r2, #1024 ; 0x400
800221e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8002220: 68fb ldr r3, [r7, #12]
8002222: 681b ldr r3, [r3, #0]
8002224: 6999 ldr r1, [r3, #24]
8002226: 68bb ldr r3, [r7, #8]
8002228: 691b ldr r3, [r3, #16]
800222a: 021a lsls r2, r3, #8
800222c: 68fb ldr r3, [r7, #12]
800222e: 681b ldr r3, [r3, #0]
8002230: 430a orrs r2, r1
8002232: 619a str r2, [r3, #24]
break;
8002234: e043 b.n 80022be <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002236: 68fb ldr r3, [r7, #12]
8002238: 681b ldr r3, [r3, #0]
800223a: 68b9 ldr r1, [r7, #8]
800223c: 4618 mov r0, r3
800223e: f000 fa89 bl 8002754 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8002242: 68fb ldr r3, [r7, #12]
8002244: 681b ldr r3, [r3, #0]
8002246: 69da ldr r2, [r3, #28]
8002248: 68fb ldr r3, [r7, #12]
800224a: 681b ldr r3, [r3, #0]
800224c: f042 0208 orr.w r2, r2, #8
8002250: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8002252: 68fb ldr r3, [r7, #12]
8002254: 681b ldr r3, [r3, #0]
8002256: 69da ldr r2, [r3, #28]
8002258: 68fb ldr r3, [r7, #12]
800225a: 681b ldr r3, [r3, #0]
800225c: f022 0204 bic.w r2, r2, #4
8002260: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8002262: 68fb ldr r3, [r7, #12]
8002264: 681b ldr r3, [r3, #0]
8002266: 69d9 ldr r1, [r3, #28]
8002268: 68bb ldr r3, [r7, #8]
800226a: 691a ldr r2, [r3, #16]
800226c: 68fb ldr r3, [r7, #12]
800226e: 681b ldr r3, [r3, #0]
8002270: 430a orrs r2, r1
8002272: 61da str r2, [r3, #28]
break;
8002274: e023 b.n 80022be <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002276: 68fb ldr r3, [r7, #12]
8002278: 681b ldr r3, [r3, #0]
800227a: 68b9 ldr r1, [r7, #8]
800227c: 4618 mov r0, r3
800227e: f000 fad3 bl 8002828 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8002282: 68fb ldr r3, [r7, #12]
8002284: 681b ldr r3, [r3, #0]
8002286: 69da ldr r2, [r3, #28]
8002288: 68fb ldr r3, [r7, #12]
800228a: 681b ldr r3, [r3, #0]
800228c: f442 6200 orr.w r2, r2, #2048 ; 0x800
8002290: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8002292: 68fb ldr r3, [r7, #12]
8002294: 681b ldr r3, [r3, #0]
8002296: 69da ldr r2, [r3, #28]
8002298: 68fb ldr r3, [r7, #12]
800229a: 681b ldr r3, [r3, #0]
800229c: f422 6280 bic.w r2, r2, #1024 ; 0x400
80022a0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
80022a2: 68fb ldr r3, [r7, #12]
80022a4: 681b ldr r3, [r3, #0]
80022a6: 69d9 ldr r1, [r3, #28]
80022a8: 68bb ldr r3, [r7, #8]
80022aa: 691b ldr r3, [r3, #16]
80022ac: 021a lsls r2, r3, #8
80022ae: 68fb ldr r3, [r7, #12]
80022b0: 681b ldr r3, [r3, #0]
80022b2: 430a orrs r2, r1
80022b4: 61da str r2, [r3, #28]
break;
80022b6: e002 b.n 80022be <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
80022b8: 2301 movs r3, #1
80022ba: 75fb strb r3, [r7, #23]
break;
80022bc: bf00 nop
}
__HAL_UNLOCK(htim);
80022be: 68fb ldr r3, [r7, #12]
80022c0: 2200 movs r2, #0
80022c2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
80022c6: 7dfb ldrb r3, [r7, #23]
}
80022c8: 4618 mov r0, r3
80022ca: 3718 adds r7, #24
80022cc: 46bd mov sp, r7
80022ce: bd80 pop {r7, pc}
080022d0 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80022d0: b580 push {r7, lr}
80022d2: b084 sub sp, #16
80022d4: af00 add r7, sp, #0
80022d6: 6078 str r0, [r7, #4]
80022d8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80022da: 2300 movs r3, #0
80022dc: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80022de: 687b ldr r3, [r7, #4]
80022e0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80022e4: 2b01 cmp r3, #1
80022e6: d101 bne.n 80022ec <HAL_TIM_ConfigClockSource+0x1c>
80022e8: 2302 movs r3, #2
80022ea: e0b4 b.n 8002456 <HAL_TIM_ConfigClockSource+0x186>
80022ec: 687b ldr r3, [r7, #4]
80022ee: 2201 movs r2, #1
80022f0: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80022f4: 687b ldr r3, [r7, #4]
80022f6: 2202 movs r2, #2
80022f8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80022fc: 687b ldr r3, [r7, #4]
80022fe: 681b ldr r3, [r3, #0]
8002300: 689b ldr r3, [r3, #8]
8002302: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8002304: 68bb ldr r3, [r7, #8]
8002306: f023 0377 bic.w r3, r3, #119 ; 0x77
800230a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800230c: 68bb ldr r3, [r7, #8]
800230e: f423 437f bic.w r3, r3, #65280 ; 0xff00
8002312: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8002314: 687b ldr r3, [r7, #4]
8002316: 681b ldr r3, [r3, #0]
8002318: 68ba ldr r2, [r7, #8]
800231a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800231c: 683b ldr r3, [r7, #0]
800231e: 681b ldr r3, [r3, #0]
8002320: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8002324: d03e beq.n 80023a4 <HAL_TIM_ConfigClockSource+0xd4>
8002326: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800232a: f200 8087 bhi.w 800243c <HAL_TIM_ConfigClockSource+0x16c>
800232e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002332: f000 8086 beq.w 8002442 <HAL_TIM_ConfigClockSource+0x172>
8002336: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800233a: d87f bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
800233c: 2b70 cmp r3, #112 ; 0x70
800233e: d01a beq.n 8002376 <HAL_TIM_ConfigClockSource+0xa6>
8002340: 2b70 cmp r3, #112 ; 0x70
8002342: d87b bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
8002344: 2b60 cmp r3, #96 ; 0x60
8002346: d050 beq.n 80023ea <HAL_TIM_ConfigClockSource+0x11a>
8002348: 2b60 cmp r3, #96 ; 0x60
800234a: d877 bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
800234c: 2b50 cmp r3, #80 ; 0x50
800234e: d03c beq.n 80023ca <HAL_TIM_ConfigClockSource+0xfa>
8002350: 2b50 cmp r3, #80 ; 0x50
8002352: d873 bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
8002354: 2b40 cmp r3, #64 ; 0x40
8002356: d058 beq.n 800240a <HAL_TIM_ConfigClockSource+0x13a>
8002358: 2b40 cmp r3, #64 ; 0x40
800235a: d86f bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
800235c: 2b30 cmp r3, #48 ; 0x30
800235e: d064 beq.n 800242a <HAL_TIM_ConfigClockSource+0x15a>
8002360: 2b30 cmp r3, #48 ; 0x30
8002362: d86b bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
8002364: 2b20 cmp r3, #32
8002366: d060 beq.n 800242a <HAL_TIM_ConfigClockSource+0x15a>
8002368: 2b20 cmp r3, #32
800236a: d867 bhi.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
800236c: 2b00 cmp r3, #0
800236e: d05c beq.n 800242a <HAL_TIM_ConfigClockSource+0x15a>
8002370: 2b10 cmp r3, #16
8002372: d05a beq.n 800242a <HAL_TIM_ConfigClockSource+0x15a>
8002374: e062 b.n 800243c <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8002376: 687b ldr r3, [r7, #4]
8002378: 6818 ldr r0, [r3, #0]
800237a: 683b ldr r3, [r7, #0]
800237c: 6899 ldr r1, [r3, #8]
800237e: 683b ldr r3, [r7, #0]
8002380: 685a ldr r2, [r3, #4]
8002382: 683b ldr r3, [r7, #0]
8002384: 68db ldr r3, [r3, #12]
8002386: f000 fb19 bl 80029bc <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800238a: 687b ldr r3, [r7, #4]
800238c: 681b ldr r3, [r3, #0]
800238e: 689b ldr r3, [r3, #8]
8002390: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8002392: 68bb ldr r3, [r7, #8]
8002394: f043 0377 orr.w r3, r3, #119 ; 0x77
8002398: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800239a: 687b ldr r3, [r7, #4]
800239c: 681b ldr r3, [r3, #0]
800239e: 68ba ldr r2, [r7, #8]
80023a0: 609a str r2, [r3, #8]
break;
80023a2: e04f b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80023a4: 687b ldr r3, [r7, #4]
80023a6: 6818 ldr r0, [r3, #0]
80023a8: 683b ldr r3, [r7, #0]
80023aa: 6899 ldr r1, [r3, #8]
80023ac: 683b ldr r3, [r7, #0]
80023ae: 685a ldr r2, [r3, #4]
80023b0: 683b ldr r3, [r7, #0]
80023b2: 68db ldr r3, [r3, #12]
80023b4: f000 fb02 bl 80029bc <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
80023b8: 687b ldr r3, [r7, #4]
80023ba: 681b ldr r3, [r3, #0]
80023bc: 689a ldr r2, [r3, #8]
80023be: 687b ldr r3, [r7, #4]
80023c0: 681b ldr r3, [r3, #0]
80023c2: f442 4280 orr.w r2, r2, #16384 ; 0x4000
80023c6: 609a str r2, [r3, #8]
break;
80023c8: e03c b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80023ca: 687b ldr r3, [r7, #4]
80023cc: 6818 ldr r0, [r3, #0]
80023ce: 683b ldr r3, [r7, #0]
80023d0: 6859 ldr r1, [r3, #4]
80023d2: 683b ldr r3, [r7, #0]
80023d4: 68db ldr r3, [r3, #12]
80023d6: 461a mov r2, r3
80023d8: f000 fa76 bl 80028c8 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80023dc: 687b ldr r3, [r7, #4]
80023de: 681b ldr r3, [r3, #0]
80023e0: 2150 movs r1, #80 ; 0x50
80023e2: 4618 mov r0, r3
80023e4: f000 facf bl 8002986 <TIM_ITRx_SetConfig>
break;
80023e8: e02c b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80023ea: 687b ldr r3, [r7, #4]
80023ec: 6818 ldr r0, [r3, #0]
80023ee: 683b ldr r3, [r7, #0]
80023f0: 6859 ldr r1, [r3, #4]
80023f2: 683b ldr r3, [r7, #0]
80023f4: 68db ldr r3, [r3, #12]
80023f6: 461a mov r2, r3
80023f8: f000 fa95 bl 8002926 <TIM_TI2_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80023fc: 687b ldr r3, [r7, #4]
80023fe: 681b ldr r3, [r3, #0]
8002400: 2160 movs r1, #96 ; 0x60
8002402: 4618 mov r0, r3
8002404: f000 fabf bl 8002986 <TIM_ITRx_SetConfig>
break;
8002408: e01c b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800240a: 687b ldr r3, [r7, #4]
800240c: 6818 ldr r0, [r3, #0]
800240e: 683b ldr r3, [r7, #0]
8002410: 6859 ldr r1, [r3, #4]
8002412: 683b ldr r3, [r7, #0]
8002414: 68db ldr r3, [r3, #12]
8002416: 461a mov r2, r3
8002418: f000 fa56 bl 80028c8 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800241c: 687b ldr r3, [r7, #4]
800241e: 681b ldr r3, [r3, #0]
8002420: 2140 movs r1, #64 ; 0x40
8002422: 4618 mov r0, r3
8002424: f000 faaf bl 8002986 <TIM_ITRx_SetConfig>
break;
8002428: e00c b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800242a: 687b ldr r3, [r7, #4]
800242c: 681a ldr r2, [r3, #0]
800242e: 683b ldr r3, [r7, #0]
8002430: 681b ldr r3, [r3, #0]
8002432: 4619 mov r1, r3
8002434: 4610 mov r0, r2
8002436: f000 faa6 bl 8002986 <TIM_ITRx_SetConfig>
break;
800243a: e003 b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
800243c: 2301 movs r3, #1
800243e: 73fb strb r3, [r7, #15]
break;
8002440: e000 b.n 8002444 <HAL_TIM_ConfigClockSource+0x174>
break;
8002442: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8002444: 687b ldr r3, [r7, #4]
8002446: 2201 movs r2, #1
8002448: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800244c: 687b ldr r3, [r7, #4]
800244e: 2200 movs r2, #0
8002450: f883 203c strb.w r2, [r3, #60] ; 0x3c
return status;
8002454: 7bfb ldrb r3, [r7, #15]
}
8002456: 4618 mov r0, r3
8002458: 3710 adds r7, #16
800245a: 46bd mov sp, r7
800245c: bd80 pop {r7, pc}
0800245e <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800245e: b480 push {r7}
8002460: b083 sub sp, #12
8002462: af00 add r7, sp, #0
8002464: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8002466: bf00 nop
8002468: 370c adds r7, #12
800246a: 46bd mov sp, r7
800246c: f85d 7b04 ldr.w r7, [sp], #4
8002470: 4770 bx lr
08002472 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8002472: b480 push {r7}
8002474: b083 sub sp, #12
8002476: af00 add r7, sp, #0
8002478: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800247a: bf00 nop
800247c: 370c adds r7, #12
800247e: 46bd mov sp, r7
8002480: f85d 7b04 ldr.w r7, [sp], #4
8002484: 4770 bx lr
08002486 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8002486: b480 push {r7}
8002488: b083 sub sp, #12
800248a: af00 add r7, sp, #0
800248c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800248e: bf00 nop
8002490: 370c adds r7, #12
8002492: 46bd mov sp, r7
8002494: f85d 7b04 ldr.w r7, [sp], #4
8002498: 4770 bx lr
0800249a <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800249a: b480 push {r7}
800249c: b083 sub sp, #12
800249e: af00 add r7, sp, #0
80024a0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80024a2: bf00 nop
80024a4: 370c adds r7, #12
80024a6: 46bd mov sp, r7
80024a8: f85d 7b04 ldr.w r7, [sp], #4
80024ac: 4770 bx lr
...
080024b0 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
80024b0: b480 push {r7}
80024b2: b085 sub sp, #20
80024b4: af00 add r7, sp, #0
80024b6: 6078 str r0, [r7, #4]
80024b8: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80024ba: 687b ldr r3, [r7, #4]
80024bc: 681b ldr r3, [r3, #0]
80024be: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80024c0: 687b ldr r3, [r7, #4]
80024c2: 4a34 ldr r2, [pc, #208] ; (8002594 <TIM_Base_SetConfig+0xe4>)
80024c4: 4293 cmp r3, r2
80024c6: d00f beq.n 80024e8 <TIM_Base_SetConfig+0x38>
80024c8: 687b ldr r3, [r7, #4]
80024ca: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80024ce: d00b beq.n 80024e8 <TIM_Base_SetConfig+0x38>
80024d0: 687b ldr r3, [r7, #4]
80024d2: 4a31 ldr r2, [pc, #196] ; (8002598 <TIM_Base_SetConfig+0xe8>)
80024d4: 4293 cmp r3, r2
80024d6: d007 beq.n 80024e8 <TIM_Base_SetConfig+0x38>
80024d8: 687b ldr r3, [r7, #4]
80024da: 4a30 ldr r2, [pc, #192] ; (800259c <TIM_Base_SetConfig+0xec>)
80024dc: 4293 cmp r3, r2
80024de: d003 beq.n 80024e8 <TIM_Base_SetConfig+0x38>
80024e0: 687b ldr r3, [r7, #4]
80024e2: 4a2f ldr r2, [pc, #188] ; (80025a0 <TIM_Base_SetConfig+0xf0>)
80024e4: 4293 cmp r3, r2
80024e6: d108 bne.n 80024fa <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80024e8: 68fb ldr r3, [r7, #12]
80024ea: f023 0370 bic.w r3, r3, #112 ; 0x70
80024ee: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80024f0: 683b ldr r3, [r7, #0]
80024f2: 685b ldr r3, [r3, #4]
80024f4: 68fa ldr r2, [r7, #12]
80024f6: 4313 orrs r3, r2
80024f8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80024fa: 687b ldr r3, [r7, #4]
80024fc: 4a25 ldr r2, [pc, #148] ; (8002594 <TIM_Base_SetConfig+0xe4>)
80024fe: 4293 cmp r3, r2
8002500: d01b beq.n 800253a <TIM_Base_SetConfig+0x8a>
8002502: 687b ldr r3, [r7, #4]
8002504: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002508: d017 beq.n 800253a <TIM_Base_SetConfig+0x8a>
800250a: 687b ldr r3, [r7, #4]
800250c: 4a22 ldr r2, [pc, #136] ; (8002598 <TIM_Base_SetConfig+0xe8>)
800250e: 4293 cmp r3, r2
8002510: d013 beq.n 800253a <TIM_Base_SetConfig+0x8a>
8002512: 687b ldr r3, [r7, #4]
8002514: 4a21 ldr r2, [pc, #132] ; (800259c <TIM_Base_SetConfig+0xec>)
8002516: 4293 cmp r3, r2
8002518: d00f beq.n 800253a <TIM_Base_SetConfig+0x8a>
800251a: 687b ldr r3, [r7, #4]
800251c: 4a20 ldr r2, [pc, #128] ; (80025a0 <TIM_Base_SetConfig+0xf0>)
800251e: 4293 cmp r3, r2
8002520: d00b beq.n 800253a <TIM_Base_SetConfig+0x8a>
8002522: 687b ldr r3, [r7, #4]
8002524: 4a1f ldr r2, [pc, #124] ; (80025a4 <TIM_Base_SetConfig+0xf4>)
8002526: 4293 cmp r3, r2
8002528: d007 beq.n 800253a <TIM_Base_SetConfig+0x8a>
800252a: 687b ldr r3, [r7, #4]
800252c: 4a1e ldr r2, [pc, #120] ; (80025a8 <TIM_Base_SetConfig+0xf8>)
800252e: 4293 cmp r3, r2
8002530: d003 beq.n 800253a <TIM_Base_SetConfig+0x8a>
8002532: 687b ldr r3, [r7, #4]
8002534: 4a1d ldr r2, [pc, #116] ; (80025ac <TIM_Base_SetConfig+0xfc>)
8002536: 4293 cmp r3, r2
8002538: d108 bne.n 800254c <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800253a: 68fb ldr r3, [r7, #12]
800253c: f423 7340 bic.w r3, r3, #768 ; 0x300
8002540: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8002542: 683b ldr r3, [r7, #0]
8002544: 68db ldr r3, [r3, #12]
8002546: 68fa ldr r2, [r7, #12]
8002548: 4313 orrs r3, r2
800254a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800254c: 68fb ldr r3, [r7, #12]
800254e: f023 0280 bic.w r2, r3, #128 ; 0x80
8002552: 683b ldr r3, [r7, #0]
8002554: 695b ldr r3, [r3, #20]
8002556: 4313 orrs r3, r2
8002558: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800255a: 687b ldr r3, [r7, #4]
800255c: 68fa ldr r2, [r7, #12]
800255e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8002560: 683b ldr r3, [r7, #0]
8002562: 689a ldr r2, [r3, #8]
8002564: 687b ldr r3, [r7, #4]
8002566: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8002568: 683b ldr r3, [r7, #0]
800256a: 681a ldr r2, [r3, #0]
800256c: 687b ldr r3, [r7, #4]
800256e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8002570: 687b ldr r3, [r7, #4]
8002572: 4a08 ldr r2, [pc, #32] ; (8002594 <TIM_Base_SetConfig+0xe4>)
8002574: 4293 cmp r3, r2
8002576: d103 bne.n 8002580 <TIM_Base_SetConfig+0xd0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8002578: 683b ldr r3, [r7, #0]
800257a: 691a ldr r2, [r3, #16]
800257c: 687b ldr r3, [r7, #4]
800257e: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8002580: 687b ldr r3, [r7, #4]
8002582: 2201 movs r2, #1
8002584: 615a str r2, [r3, #20]
}
8002586: bf00 nop
8002588: 3714 adds r7, #20
800258a: 46bd mov sp, r7
800258c: f85d 7b04 ldr.w r7, [sp], #4
8002590: 4770 bx lr
8002592: bf00 nop
8002594: 40010000 .word 0x40010000
8002598: 40000400 .word 0x40000400
800259c: 40000800 .word 0x40000800
80025a0: 40000c00 .word 0x40000c00
80025a4: 40014000 .word 0x40014000
80025a8: 40014400 .word 0x40014400
80025ac: 40014800 .word 0x40014800
080025b0 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80025b0: b480 push {r7}
80025b2: b087 sub sp, #28
80025b4: af00 add r7, sp, #0
80025b6: 6078 str r0, [r7, #4]
80025b8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80025ba: 687b ldr r3, [r7, #4]
80025bc: 6a1b ldr r3, [r3, #32]
80025be: f023 0201 bic.w r2, r3, #1
80025c2: 687b ldr r3, [r7, #4]
80025c4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80025c6: 687b ldr r3, [r7, #4]
80025c8: 6a1b ldr r3, [r3, #32]
80025ca: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80025cc: 687b ldr r3, [r7, #4]
80025ce: 685b ldr r3, [r3, #4]
80025d0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80025d2: 687b ldr r3, [r7, #4]
80025d4: 699b ldr r3, [r3, #24]
80025d6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80025d8: 68fb ldr r3, [r7, #12]
80025da: f023 0370 bic.w r3, r3, #112 ; 0x70
80025de: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80025e0: 68fb ldr r3, [r7, #12]
80025e2: f023 0303 bic.w r3, r3, #3
80025e6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80025e8: 683b ldr r3, [r7, #0]
80025ea: 681b ldr r3, [r3, #0]
80025ec: 68fa ldr r2, [r7, #12]
80025ee: 4313 orrs r3, r2
80025f0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
80025f2: 697b ldr r3, [r7, #20]
80025f4: f023 0302 bic.w r3, r3, #2
80025f8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
80025fa: 683b ldr r3, [r7, #0]
80025fc: 689b ldr r3, [r3, #8]
80025fe: 697a ldr r2, [r7, #20]
8002600: 4313 orrs r3, r2
8002602: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8002604: 687b ldr r3, [r7, #4]
8002606: 4a1c ldr r2, [pc, #112] ; (8002678 <TIM_OC1_SetConfig+0xc8>)
8002608: 4293 cmp r3, r2
800260a: d10c bne.n 8002626 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800260c: 697b ldr r3, [r7, #20]
800260e: f023 0308 bic.w r3, r3, #8
8002612: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8002614: 683b ldr r3, [r7, #0]
8002616: 68db ldr r3, [r3, #12]
8002618: 697a ldr r2, [r7, #20]
800261a: 4313 orrs r3, r2
800261c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800261e: 697b ldr r3, [r7, #20]
8002620: f023 0304 bic.w r3, r3, #4
8002624: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002626: 687b ldr r3, [r7, #4]
8002628: 4a13 ldr r2, [pc, #76] ; (8002678 <TIM_OC1_SetConfig+0xc8>)
800262a: 4293 cmp r3, r2
800262c: d111 bne.n 8002652 <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800262e: 693b ldr r3, [r7, #16]
8002630: f423 7380 bic.w r3, r3, #256 ; 0x100
8002634: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8002636: 693b ldr r3, [r7, #16]
8002638: f423 7300 bic.w r3, r3, #512 ; 0x200
800263c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800263e: 683b ldr r3, [r7, #0]
8002640: 695b ldr r3, [r3, #20]
8002642: 693a ldr r2, [r7, #16]
8002644: 4313 orrs r3, r2
8002646: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8002648: 683b ldr r3, [r7, #0]
800264a: 699b ldr r3, [r3, #24]
800264c: 693a ldr r2, [r7, #16]
800264e: 4313 orrs r3, r2
8002650: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002652: 687b ldr r3, [r7, #4]
8002654: 693a ldr r2, [r7, #16]
8002656: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8002658: 687b ldr r3, [r7, #4]
800265a: 68fa ldr r2, [r7, #12]
800265c: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800265e: 683b ldr r3, [r7, #0]
8002660: 685a ldr r2, [r3, #4]
8002662: 687b ldr r3, [r7, #4]
8002664: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002666: 687b ldr r3, [r7, #4]
8002668: 697a ldr r2, [r7, #20]
800266a: 621a str r2, [r3, #32]
}
800266c: bf00 nop
800266e: 371c adds r7, #28
8002670: 46bd mov sp, r7
8002672: f85d 7b04 ldr.w r7, [sp], #4
8002676: 4770 bx lr
8002678: 40010000 .word 0x40010000
0800267c <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800267c: b480 push {r7}
800267e: b087 sub sp, #28
8002680: af00 add r7, sp, #0
8002682: 6078 str r0, [r7, #4]
8002684: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8002686: 687b ldr r3, [r7, #4]
8002688: 6a1b ldr r3, [r3, #32]
800268a: f023 0210 bic.w r2, r3, #16
800268e: 687b ldr r3, [r7, #4]
8002690: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002692: 687b ldr r3, [r7, #4]
8002694: 6a1b ldr r3, [r3, #32]
8002696: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002698: 687b ldr r3, [r7, #4]
800269a: 685b ldr r3, [r3, #4]
800269c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800269e: 687b ldr r3, [r7, #4]
80026a0: 699b ldr r3, [r3, #24]
80026a2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
80026a4: 68fb ldr r3, [r7, #12]
80026a6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80026aa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
80026ac: 68fb ldr r3, [r7, #12]
80026ae: f423 7340 bic.w r3, r3, #768 ; 0x300
80026b2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80026b4: 683b ldr r3, [r7, #0]
80026b6: 681b ldr r3, [r3, #0]
80026b8: 021b lsls r3, r3, #8
80026ba: 68fa ldr r2, [r7, #12]
80026bc: 4313 orrs r3, r2
80026be: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
80026c0: 697b ldr r3, [r7, #20]
80026c2: f023 0320 bic.w r3, r3, #32
80026c6: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
80026c8: 683b ldr r3, [r7, #0]
80026ca: 689b ldr r3, [r3, #8]
80026cc: 011b lsls r3, r3, #4
80026ce: 697a ldr r2, [r7, #20]
80026d0: 4313 orrs r3, r2
80026d2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
80026d4: 687b ldr r3, [r7, #4]
80026d6: 4a1e ldr r2, [pc, #120] ; (8002750 <TIM_OC2_SetConfig+0xd4>)
80026d8: 4293 cmp r3, r2
80026da: d10d bne.n 80026f8 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
80026dc: 697b ldr r3, [r7, #20]
80026de: f023 0380 bic.w r3, r3, #128 ; 0x80
80026e2: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
80026e4: 683b ldr r3, [r7, #0]
80026e6: 68db ldr r3, [r3, #12]
80026e8: 011b lsls r3, r3, #4
80026ea: 697a ldr r2, [r7, #20]
80026ec: 4313 orrs r3, r2
80026ee: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
80026f0: 697b ldr r3, [r7, #20]
80026f2: f023 0340 bic.w r3, r3, #64 ; 0x40
80026f6: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80026f8: 687b ldr r3, [r7, #4]
80026fa: 4a15 ldr r2, [pc, #84] ; (8002750 <TIM_OC2_SetConfig+0xd4>)
80026fc: 4293 cmp r3, r2
80026fe: d113 bne.n 8002728 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8002700: 693b ldr r3, [r7, #16]
8002702: f423 6380 bic.w r3, r3, #1024 ; 0x400
8002706: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8002708: 693b ldr r3, [r7, #16]
800270a: f423 6300 bic.w r3, r3, #2048 ; 0x800
800270e: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8002710: 683b ldr r3, [r7, #0]
8002712: 695b ldr r3, [r3, #20]
8002714: 009b lsls r3, r3, #2
8002716: 693a ldr r2, [r7, #16]
8002718: 4313 orrs r3, r2
800271a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800271c: 683b ldr r3, [r7, #0]
800271e: 699b ldr r3, [r3, #24]
8002720: 009b lsls r3, r3, #2
8002722: 693a ldr r2, [r7, #16]
8002724: 4313 orrs r3, r2
8002726: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002728: 687b ldr r3, [r7, #4]
800272a: 693a ldr r2, [r7, #16]
800272c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800272e: 687b ldr r3, [r7, #4]
8002730: 68fa ldr r2, [r7, #12]
8002732: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8002734: 683b ldr r3, [r7, #0]
8002736: 685a ldr r2, [r3, #4]
8002738: 687b ldr r3, [r7, #4]
800273a: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800273c: 687b ldr r3, [r7, #4]
800273e: 697a ldr r2, [r7, #20]
8002740: 621a str r2, [r3, #32]
}
8002742: bf00 nop
8002744: 371c adds r7, #28
8002746: 46bd mov sp, r7
8002748: f85d 7b04 ldr.w r7, [sp], #4
800274c: 4770 bx lr
800274e: bf00 nop
8002750: 40010000 .word 0x40010000
08002754 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002754: b480 push {r7}
8002756: b087 sub sp, #28
8002758: af00 add r7, sp, #0
800275a: 6078 str r0, [r7, #4]
800275c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800275e: 687b ldr r3, [r7, #4]
8002760: 6a1b ldr r3, [r3, #32]
8002762: f423 7280 bic.w r2, r3, #256 ; 0x100
8002766: 687b ldr r3, [r7, #4]
8002768: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800276a: 687b ldr r3, [r7, #4]
800276c: 6a1b ldr r3, [r3, #32]
800276e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002770: 687b ldr r3, [r7, #4]
8002772: 685b ldr r3, [r3, #4]
8002774: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002776: 687b ldr r3, [r7, #4]
8002778: 69db ldr r3, [r3, #28]
800277a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800277c: 68fb ldr r3, [r7, #12]
800277e: f023 0370 bic.w r3, r3, #112 ; 0x70
8002782: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8002784: 68fb ldr r3, [r7, #12]
8002786: f023 0303 bic.w r3, r3, #3
800278a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800278c: 683b ldr r3, [r7, #0]
800278e: 681b ldr r3, [r3, #0]
8002790: 68fa ldr r2, [r7, #12]
8002792: 4313 orrs r3, r2
8002794: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8002796: 697b ldr r3, [r7, #20]
8002798: f423 7300 bic.w r3, r3, #512 ; 0x200
800279c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
800279e: 683b ldr r3, [r7, #0]
80027a0: 689b ldr r3, [r3, #8]
80027a2: 021b lsls r3, r3, #8
80027a4: 697a ldr r2, [r7, #20]
80027a6: 4313 orrs r3, r2
80027a8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
80027aa: 687b ldr r3, [r7, #4]
80027ac: 4a1d ldr r2, [pc, #116] ; (8002824 <TIM_OC3_SetConfig+0xd0>)
80027ae: 4293 cmp r3, r2
80027b0: d10d bne.n 80027ce <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80027b2: 697b ldr r3, [r7, #20]
80027b4: f423 6300 bic.w r3, r3, #2048 ; 0x800
80027b8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80027ba: 683b ldr r3, [r7, #0]
80027bc: 68db ldr r3, [r3, #12]
80027be: 021b lsls r3, r3, #8
80027c0: 697a ldr r2, [r7, #20]
80027c2: 4313 orrs r3, r2
80027c4: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80027c6: 697b ldr r3, [r7, #20]
80027c8: f423 6380 bic.w r3, r3, #1024 ; 0x400
80027cc: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80027ce: 687b ldr r3, [r7, #4]
80027d0: 4a14 ldr r2, [pc, #80] ; (8002824 <TIM_OC3_SetConfig+0xd0>)
80027d2: 4293 cmp r3, r2
80027d4: d113 bne.n 80027fe <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80027d6: 693b ldr r3, [r7, #16]
80027d8: f423 5380 bic.w r3, r3, #4096 ; 0x1000
80027dc: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
80027de: 693b ldr r3, [r7, #16]
80027e0: f423 5300 bic.w r3, r3, #8192 ; 0x2000
80027e4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
80027e6: 683b ldr r3, [r7, #0]
80027e8: 695b ldr r3, [r3, #20]
80027ea: 011b lsls r3, r3, #4
80027ec: 693a ldr r2, [r7, #16]
80027ee: 4313 orrs r3, r2
80027f0: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
80027f2: 683b ldr r3, [r7, #0]
80027f4: 699b ldr r3, [r3, #24]
80027f6: 011b lsls r3, r3, #4
80027f8: 693a ldr r2, [r7, #16]
80027fa: 4313 orrs r3, r2
80027fc: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80027fe: 687b ldr r3, [r7, #4]
8002800: 693a ldr r2, [r7, #16]
8002802: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002804: 687b ldr r3, [r7, #4]
8002806: 68fa ldr r2, [r7, #12]
8002808: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800280a: 683b ldr r3, [r7, #0]
800280c: 685a ldr r2, [r3, #4]
800280e: 687b ldr r3, [r7, #4]
8002810: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002812: 687b ldr r3, [r7, #4]
8002814: 697a ldr r2, [r7, #20]
8002816: 621a str r2, [r3, #32]
}
8002818: bf00 nop
800281a: 371c adds r7, #28
800281c: 46bd mov sp, r7
800281e: f85d 7b04 ldr.w r7, [sp], #4
8002822: 4770 bx lr
8002824: 40010000 .word 0x40010000
08002828 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8002828: b480 push {r7}
800282a: b087 sub sp, #28
800282c: af00 add r7, sp, #0
800282e: 6078 str r0, [r7, #4]
8002830: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8002832: 687b ldr r3, [r7, #4]
8002834: 6a1b ldr r3, [r3, #32]
8002836: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800283a: 687b ldr r3, [r7, #4]
800283c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800283e: 687b ldr r3, [r7, #4]
8002840: 6a1b ldr r3, [r3, #32]
8002842: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002844: 687b ldr r3, [r7, #4]
8002846: 685b ldr r3, [r3, #4]
8002848: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800284a: 687b ldr r3, [r7, #4]
800284c: 69db ldr r3, [r3, #28]
800284e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8002850: 68fb ldr r3, [r7, #12]
8002852: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8002856: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8002858: 68fb ldr r3, [r7, #12]
800285a: f423 7340 bic.w r3, r3, #768 ; 0x300
800285e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002860: 683b ldr r3, [r7, #0]
8002862: 681b ldr r3, [r3, #0]
8002864: 021b lsls r3, r3, #8
8002866: 68fa ldr r2, [r7, #12]
8002868: 4313 orrs r3, r2
800286a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800286c: 693b ldr r3, [r7, #16]
800286e: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8002872: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8002874: 683b ldr r3, [r7, #0]
8002876: 689b ldr r3, [r3, #8]
8002878: 031b lsls r3, r3, #12
800287a: 693a ldr r2, [r7, #16]
800287c: 4313 orrs r3, r2
800287e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002880: 687b ldr r3, [r7, #4]
8002882: 4a10 ldr r2, [pc, #64] ; (80028c4 <TIM_OC4_SetConfig+0x9c>)
8002884: 4293 cmp r3, r2
8002886: d109 bne.n 800289c <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8002888: 697b ldr r3, [r7, #20]
800288a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800288e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8002890: 683b ldr r3, [r7, #0]
8002892: 695b ldr r3, [r3, #20]
8002894: 019b lsls r3, r3, #6
8002896: 697a ldr r2, [r7, #20]
8002898: 4313 orrs r3, r2
800289a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800289c: 687b ldr r3, [r7, #4]
800289e: 697a ldr r2, [r7, #20]
80028a0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80028a2: 687b ldr r3, [r7, #4]
80028a4: 68fa ldr r2, [r7, #12]
80028a6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80028a8: 683b ldr r3, [r7, #0]
80028aa: 685a ldr r2, [r3, #4]
80028ac: 687b ldr r3, [r7, #4]
80028ae: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80028b0: 687b ldr r3, [r7, #4]
80028b2: 693a ldr r2, [r7, #16]
80028b4: 621a str r2, [r3, #32]
}
80028b6: bf00 nop
80028b8: 371c adds r7, #28
80028ba: 46bd mov sp, r7
80028bc: f85d 7b04 ldr.w r7, [sp], #4
80028c0: 4770 bx lr
80028c2: bf00 nop
80028c4: 40010000 .word 0x40010000
080028c8 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80028c8: b480 push {r7}
80028ca: b087 sub sp, #28
80028cc: af00 add r7, sp, #0
80028ce: 60f8 str r0, [r7, #12]
80028d0: 60b9 str r1, [r7, #8]
80028d2: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80028d4: 68fb ldr r3, [r7, #12]
80028d6: 6a1b ldr r3, [r3, #32]
80028d8: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
80028da: 68fb ldr r3, [r7, #12]
80028dc: 6a1b ldr r3, [r3, #32]
80028de: f023 0201 bic.w r2, r3, #1
80028e2: 68fb ldr r3, [r7, #12]
80028e4: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80028e6: 68fb ldr r3, [r7, #12]
80028e8: 699b ldr r3, [r3, #24]
80028ea: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
80028ec: 693b ldr r3, [r7, #16]
80028ee: f023 03f0 bic.w r3, r3, #240 ; 0xf0
80028f2: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
80028f4: 687b ldr r3, [r7, #4]
80028f6: 011b lsls r3, r3, #4
80028f8: 693a ldr r2, [r7, #16]
80028fa: 4313 orrs r3, r2
80028fc: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
80028fe: 697b ldr r3, [r7, #20]
8002900: f023 030a bic.w r3, r3, #10
8002904: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8002906: 697a ldr r2, [r7, #20]
8002908: 68bb ldr r3, [r7, #8]
800290a: 4313 orrs r3, r2
800290c: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800290e: 68fb ldr r3, [r7, #12]
8002910: 693a ldr r2, [r7, #16]
8002912: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002914: 68fb ldr r3, [r7, #12]
8002916: 697a ldr r2, [r7, #20]
8002918: 621a str r2, [r3, #32]
}
800291a: bf00 nop
800291c: 371c adds r7, #28
800291e: 46bd mov sp, r7
8002920: f85d 7b04 ldr.w r7, [sp], #4
8002924: 4770 bx lr
08002926 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8002926: b480 push {r7}
8002928: b087 sub sp, #28
800292a: af00 add r7, sp, #0
800292c: 60f8 str r0, [r7, #12]
800292e: 60b9 str r1, [r7, #8]
8002930: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8002932: 68fb ldr r3, [r7, #12]
8002934: 6a1b ldr r3, [r3, #32]
8002936: f023 0210 bic.w r2, r3, #16
800293a: 68fb ldr r3, [r7, #12]
800293c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800293e: 68fb ldr r3, [r7, #12]
8002940: 699b ldr r3, [r3, #24]
8002942: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8002944: 68fb ldr r3, [r7, #12]
8002946: 6a1b ldr r3, [r3, #32]
8002948: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800294a: 697b ldr r3, [r7, #20]
800294c: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8002950: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8002952: 687b ldr r3, [r7, #4]
8002954: 031b lsls r3, r3, #12
8002956: 697a ldr r2, [r7, #20]
8002958: 4313 orrs r3, r2
800295a: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800295c: 693b ldr r3, [r7, #16]
800295e: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8002962: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8002964: 68bb ldr r3, [r7, #8]
8002966: 011b lsls r3, r3, #4
8002968: 693a ldr r2, [r7, #16]
800296a: 4313 orrs r3, r2
800296c: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800296e: 68fb ldr r3, [r7, #12]
8002970: 697a ldr r2, [r7, #20]
8002972: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002974: 68fb ldr r3, [r7, #12]
8002976: 693a ldr r2, [r7, #16]
8002978: 621a str r2, [r3, #32]
}
800297a: bf00 nop
800297c: 371c adds r7, #28
800297e: 46bd mov sp, r7
8002980: f85d 7b04 ldr.w r7, [sp], #4
8002984: 4770 bx lr
08002986 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8002986: b480 push {r7}
8002988: b085 sub sp, #20
800298a: af00 add r7, sp, #0
800298c: 6078 str r0, [r7, #4]
800298e: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8002990: 687b ldr r3, [r7, #4]
8002992: 689b ldr r3, [r3, #8]
8002994: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8002996: 68fb ldr r3, [r7, #12]
8002998: f023 0370 bic.w r3, r3, #112 ; 0x70
800299c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800299e: 683a ldr r2, [r7, #0]
80029a0: 68fb ldr r3, [r7, #12]
80029a2: 4313 orrs r3, r2
80029a4: f043 0307 orr.w r3, r3, #7
80029a8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80029aa: 687b ldr r3, [r7, #4]
80029ac: 68fa ldr r2, [r7, #12]
80029ae: 609a str r2, [r3, #8]
}
80029b0: bf00 nop
80029b2: 3714 adds r7, #20
80029b4: 46bd mov sp, r7
80029b6: f85d 7b04 ldr.w r7, [sp], #4
80029ba: 4770 bx lr
080029bc <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80029bc: b480 push {r7}
80029be: b087 sub sp, #28
80029c0: af00 add r7, sp, #0
80029c2: 60f8 str r0, [r7, #12]
80029c4: 60b9 str r1, [r7, #8]
80029c6: 607a str r2, [r7, #4]
80029c8: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 689b ldr r3, [r3, #8]
80029ce: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80029d0: 697b ldr r3, [r7, #20]
80029d2: f423 437f bic.w r3, r3, #65280 ; 0xff00
80029d6: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
80029d8: 683b ldr r3, [r7, #0]
80029da: 021a lsls r2, r3, #8
80029dc: 687b ldr r3, [r7, #4]
80029de: 431a orrs r2, r3
80029e0: 68bb ldr r3, [r7, #8]
80029e2: 4313 orrs r3, r2
80029e4: 697a ldr r2, [r7, #20]
80029e6: 4313 orrs r3, r2
80029e8: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80029ea: 68fb ldr r3, [r7, #12]
80029ec: 697a ldr r2, [r7, #20]
80029ee: 609a str r2, [r3, #8]
}
80029f0: bf00 nop
80029f2: 371c adds r7, #28
80029f4: 46bd mov sp, r7
80029f6: f85d 7b04 ldr.w r7, [sp], #4
80029fa: 4770 bx lr
080029fc <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
80029fc: b480 push {r7}
80029fe: b085 sub sp, #20
8002a00: af00 add r7, sp, #0
8002a02: 6078 str r0, [r7, #4]
8002a04: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8002a06: 687b ldr r3, [r7, #4]
8002a08: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002a0c: 2b01 cmp r3, #1
8002a0e: d101 bne.n 8002a14 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8002a10: 2302 movs r3, #2
8002a12: e050 b.n 8002ab6 <HAL_TIMEx_MasterConfigSynchronization+0xba>
8002a14: 687b ldr r3, [r7, #4]
8002a16: 2201 movs r2, #1
8002a18: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8002a1c: 687b ldr r3, [r7, #4]
8002a1e: 2202 movs r2, #2
8002a20: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8002a24: 687b ldr r3, [r7, #4]
8002a26: 681b ldr r3, [r3, #0]
8002a28: 685b ldr r3, [r3, #4]
8002a2a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 681b ldr r3, [r3, #0]
8002a30: 689b ldr r3, [r3, #8]
8002a32: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8002a34: 68fb ldr r3, [r7, #12]
8002a36: f023 0370 bic.w r3, r3, #112 ; 0x70
8002a3a: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8002a3c: 683b ldr r3, [r7, #0]
8002a3e: 681b ldr r3, [r3, #0]
8002a40: 68fa ldr r2, [r7, #12]
8002a42: 4313 orrs r3, r2
8002a44: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8002a46: 687b ldr r3, [r7, #4]
8002a48: 681b ldr r3, [r3, #0]
8002a4a: 68fa ldr r2, [r7, #12]
8002a4c: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 681b ldr r3, [r3, #0]
8002a52: 4a1c ldr r2, [pc, #112] ; (8002ac4 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
8002a54: 4293 cmp r3, r2
8002a56: d018 beq.n 8002a8a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8002a58: 687b ldr r3, [r7, #4]
8002a5a: 681b ldr r3, [r3, #0]
8002a5c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002a60: d013 beq.n 8002a8a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8002a62: 687b ldr r3, [r7, #4]
8002a64: 681b ldr r3, [r3, #0]
8002a66: 4a18 ldr r2, [pc, #96] ; (8002ac8 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
8002a68: 4293 cmp r3, r2
8002a6a: d00e beq.n 8002a8a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8002a6c: 687b ldr r3, [r7, #4]
8002a6e: 681b ldr r3, [r3, #0]
8002a70: 4a16 ldr r2, [pc, #88] ; (8002acc <HAL_TIMEx_MasterConfigSynchronization+0xd0>)
8002a72: 4293 cmp r3, r2
8002a74: d009 beq.n 8002a8a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8002a76: 687b ldr r3, [r7, #4]
8002a78: 681b ldr r3, [r3, #0]
8002a7a: 4a15 ldr r2, [pc, #84] ; (8002ad0 <HAL_TIMEx_MasterConfigSynchronization+0xd4>)
8002a7c: 4293 cmp r3, r2
8002a7e: d004 beq.n 8002a8a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8002a80: 687b ldr r3, [r7, #4]
8002a82: 681b ldr r3, [r3, #0]
8002a84: 4a13 ldr r2, [pc, #76] ; (8002ad4 <HAL_TIMEx_MasterConfigSynchronization+0xd8>)
8002a86: 4293 cmp r3, r2
8002a88: d10c bne.n 8002aa4 <HAL_TIMEx_MasterConfigSynchronization+0xa8>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8002a8a: 68bb ldr r3, [r7, #8]
8002a8c: f023 0380 bic.w r3, r3, #128 ; 0x80
8002a90: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8002a92: 683b ldr r3, [r7, #0]
8002a94: 685b ldr r3, [r3, #4]
8002a96: 68ba ldr r2, [r7, #8]
8002a98: 4313 orrs r3, r2
8002a9a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8002a9c: 687b ldr r3, [r7, #4]
8002a9e: 681b ldr r3, [r3, #0]
8002aa0: 68ba ldr r2, [r7, #8]
8002aa2: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8002aa4: 687b ldr r3, [r7, #4]
8002aa6: 2201 movs r2, #1
8002aa8: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8002aac: 687b ldr r3, [r7, #4]
8002aae: 2200 movs r2, #0
8002ab0: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8002ab4: 2300 movs r3, #0
}
8002ab6: 4618 mov r0, r3
8002ab8: 3714 adds r7, #20
8002aba: 46bd mov sp, r7
8002abc: f85d 7b04 ldr.w r7, [sp], #4
8002ac0: 4770 bx lr
8002ac2: bf00 nop
8002ac4: 40010000 .word 0x40010000
8002ac8: 40000400 .word 0x40000400
8002acc: 40000800 .word 0x40000800
8002ad0: 40000c00 .word 0x40000c00
8002ad4: 40014000 .word 0x40014000
08002ad8 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8002ad8: b480 push {r7}
8002ada: b085 sub sp, #20
8002adc: af00 add r7, sp, #0
8002ade: 6078 str r0, [r7, #4]
8002ae0: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8002ae2: 2300 movs r3, #0
8002ae4: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8002ae6: 687b ldr r3, [r7, #4]
8002ae8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002aec: 2b01 cmp r3, #1
8002aee: d101 bne.n 8002af4 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8002af0: 2302 movs r3, #2
8002af2: e03d b.n 8002b70 <HAL_TIMEx_ConfigBreakDeadTime+0x98>
8002af4: 687b ldr r3, [r7, #4]
8002af6: 2201 movs r2, #1
8002af8: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8002afc: 68fb ldr r3, [r7, #12]
8002afe: f023 02ff bic.w r2, r3, #255 ; 0xff
8002b02: 683b ldr r3, [r7, #0]
8002b04: 68db ldr r3, [r3, #12]
8002b06: 4313 orrs r3, r2
8002b08: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8002b0a: 68fb ldr r3, [r7, #12]
8002b0c: f423 7240 bic.w r2, r3, #768 ; 0x300
8002b10: 683b ldr r3, [r7, #0]
8002b12: 689b ldr r3, [r3, #8]
8002b14: 4313 orrs r3, r2
8002b16: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8002b18: 68fb ldr r3, [r7, #12]
8002b1a: f423 6280 bic.w r2, r3, #1024 ; 0x400
8002b1e: 683b ldr r3, [r7, #0]
8002b20: 685b ldr r3, [r3, #4]
8002b22: 4313 orrs r3, r2
8002b24: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8002b26: 68fb ldr r3, [r7, #12]
8002b28: f423 6200 bic.w r2, r3, #2048 ; 0x800
8002b2c: 683b ldr r3, [r7, #0]
8002b2e: 681b ldr r3, [r3, #0]
8002b30: 4313 orrs r3, r2
8002b32: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8002b34: 68fb ldr r3, [r7, #12]
8002b36: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8002b3a: 683b ldr r3, [r7, #0]
8002b3c: 691b ldr r3, [r3, #16]
8002b3e: 4313 orrs r3, r2
8002b40: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8002b42: 68fb ldr r3, [r7, #12]
8002b44: f423 5200 bic.w r2, r3, #8192 ; 0x2000
8002b48: 683b ldr r3, [r7, #0]
8002b4a: 695b ldr r3, [r3, #20]
8002b4c: 4313 orrs r3, r2
8002b4e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8002b50: 68fb ldr r3, [r7, #12]
8002b52: f423 4280 bic.w r2, r3, #16384 ; 0x4000
8002b56: 683b ldr r3, [r7, #0]
8002b58: 69db ldr r3, [r3, #28]
8002b5a: 4313 orrs r3, r2
8002b5c: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8002b5e: 687b ldr r3, [r7, #4]
8002b60: 681b ldr r3, [r3, #0]
8002b62: 68fa ldr r2, [r7, #12]
8002b64: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
8002b66: 687b ldr r3, [r7, #4]
8002b68: 2200 movs r2, #0
8002b6a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8002b6e: 2300 movs r3, #0
}
8002b70: 4618 mov r0, r3
8002b72: 3714 adds r7, #20
8002b74: 46bd mov sp, r7
8002b76: f85d 7b04 ldr.w r7, [sp], #4
8002b7a: 4770 bx lr
08002b7c <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8002b7c: b480 push {r7}
8002b7e: b083 sub sp, #12
8002b80: af00 add r7, sp, #0
8002b82: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8002b84: bf00 nop
8002b86: 370c adds r7, #12
8002b88: 46bd mov sp, r7
8002b8a: f85d 7b04 ldr.w r7, [sp], #4
8002b8e: 4770 bx lr
08002b90 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8002b90: b480 push {r7}
8002b92: b083 sub sp, #12
8002b94: af00 add r7, sp, #0
8002b96: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8002b98: bf00 nop
8002b9a: 370c adds r7, #12
8002b9c: 46bd mov sp, r7
8002b9e: f85d 7b04 ldr.w r7, [sp], #4
8002ba2: 4770 bx lr
08002ba4 <__libc_init_array>:
8002ba4: b570 push {r4, r5, r6, lr}
8002ba6: 4d0d ldr r5, [pc, #52] ; (8002bdc <__libc_init_array+0x38>)
8002ba8: 4c0d ldr r4, [pc, #52] ; (8002be0 <__libc_init_array+0x3c>)
8002baa: 1b64 subs r4, r4, r5
8002bac: 10a4 asrs r4, r4, #2
8002bae: 2600 movs r6, #0
8002bb0: 42a6 cmp r6, r4
8002bb2: d109 bne.n 8002bc8 <__libc_init_array+0x24>
8002bb4: 4d0b ldr r5, [pc, #44] ; (8002be4 <__libc_init_array+0x40>)
8002bb6: 4c0c ldr r4, [pc, #48] ; (8002be8 <__libc_init_array+0x44>)
8002bb8: f000 f820 bl 8002bfc <_init>
8002bbc: 1b64 subs r4, r4, r5
8002bbe: 10a4 asrs r4, r4, #2
8002bc0: 2600 movs r6, #0
8002bc2: 42a6 cmp r6, r4
8002bc4: d105 bne.n 8002bd2 <__libc_init_array+0x2e>
8002bc6: bd70 pop {r4, r5, r6, pc}
8002bc8: f855 3b04 ldr.w r3, [r5], #4
8002bcc: 4798 blx r3
8002bce: 3601 adds r6, #1
8002bd0: e7ee b.n 8002bb0 <__libc_init_array+0xc>
8002bd2: f855 3b04 ldr.w r3, [r5], #4
8002bd6: 4798 blx r3
8002bd8: 3601 adds r6, #1
8002bda: e7f2 b.n 8002bc2 <__libc_init_array+0x1e>
8002bdc: 08002c44 .word 0x08002c44
8002be0: 08002c44 .word 0x08002c44
8002be4: 08002c44 .word 0x08002c44
8002be8: 08002c48 .word 0x08002c48
08002bec <memset>:
8002bec: 4402 add r2, r0
8002bee: 4603 mov r3, r0
8002bf0: 4293 cmp r3, r2
8002bf2: d100 bne.n 8002bf6 <memset+0xa>
8002bf4: 4770 bx lr
8002bf6: f803 1b01 strb.w r1, [r3], #1
8002bfa: e7f9 b.n 8002bf0 <memset+0x4>
08002bfc <_init>:
8002bfc: b5f8 push {r3, r4, r5, r6, r7, lr}
8002bfe: bf00 nop
8002c00: bcf8 pop {r3, r4, r5, r6, r7}
8002c02: bc08 pop {r3}
8002c04: 469e mov lr, r3
8002c06: 4770 bx lr
08002c08 <_fini>:
8002c08: b5f8 push {r3, r4, r5, r6, r7, lr}
8002c0a: bf00 nop
8002c0c: bcf8 pop {r3, r4, r5, r6, r7}
8002c0e: bc08 pop {r3}
8002c10: 469e mov lr, r3
8002c12: 4770 bx lr
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