mmc: support for CNC1800L sdio (experimental)
This commit is contained in:
haru
parent
c296381a1d
commit
a09682c8f8
@ -115,4 +115,11 @@
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// interrupts = <6>;
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cavium,nrdevs = <14>;
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};
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sdio: cncsdio@80290000{
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compatible = "cavium,cnc1800l-sdio";
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reg = <0x80290000 0x1000>;
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clocks = <&pclk>;
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interrupts = <18>;
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};
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};
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@ -55,6 +55,27 @@ config MMC_PXA
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If unsure, say N.
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config MMC_MSHCI
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tristate "Mobile Storage Host Controller Interface support"
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depends on HAS_DMA
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help
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This selects the Mobile Storage Host Controller Interface.
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If support SD/MMC card.
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If you have a controller with this interface, say Y or M here. You
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also need to enable an appropriate bus interface.
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If unsure, say N.
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config MMC_CELESTIAL
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tristate "Cavium Celestial CNC1800L SDIO"
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depends on HAS_DMA && MMC_MSHCI
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help
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This selects Cavium CNC1800L SDIO Controller.
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If support SDIO interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI
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tristate "Secure Digital Host Controller Interface support"
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depends on HAS_DMA
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@ -10,6 +10,8 @@ armmmci-$(CONFIG_MMC_STM32_SDMMC) += mmci_stm32_sdmmc.o
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obj-$(CONFIG_MMC_PXA) += pxamci.o
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obj-$(CONFIG_MMC_MXC) += mxcmmc.o
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obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
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obj-$(CONFIG_MMC_MSHCI) += mshci.o
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obj-$(CONFIG_MMC_CELESTIAL) += cnc1800l-sdio.o
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obj-$(CONFIG_MMC_SDHCI) += sdhci.o
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obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
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sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
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200
drivers/mmc/host/cnc1800l-sdio.c
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200
drivers/mmc/host/cnc1800l-sdio.c
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@ -0,0 +1,200 @@
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/*
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* Mobile Storage Host Controller Interface driver
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* Scott Shu <sshu@caviumnetworks.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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// based on mvsdio.c
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/mbus.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/of_irq.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/sizes.h>
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#include <asm/unaligned.h>
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#include "mshci.h"
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#define DRIVER_NAME "cnc1800l-sdio"
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struct cnc1800lsd_host {
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struct platform_device *pdev;
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struct mshci_host *host;
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void __iomem *base;
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unsigned long __iomem *ctrl1;
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unsigned long __iomem *ctrl2;
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struct mmc_request *mrq;
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spinlock_t lock;
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struct mmc_host *mmc;
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struct device *dev;
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struct clk *clk;
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};
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static inline struct cnc1800lsd_host *to_cnc1800l(struct mshci_host *host)
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{
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return mshci_priv(host);
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}
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static unsigned int mshci_cnc1800l_get_max_clk(struct mshci_host *host)
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{
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int clk = 47250000; /* 47.25M */
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return clk;
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}
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static void mshci_cnc1800l_set_clock(struct mshci_host *host, unsigned int clock)
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{
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/* don't bother if the clock is going off. */
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if (clock == 0)
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return;
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host->max_clk = 47250000;
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}
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static void mshci_cnc1800l_set_ios(struct mshci_host *host, struct mmc_ios *ios)
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{
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/* nothing to do */
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}
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static struct mshci_ops mshci_cnc1800l_ops = {
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.get_max_clock = mshci_cnc1800l_get_max_clk,
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.set_clock = mshci_cnc1800l_set_clock,
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.set_ios = mshci_cnc1800l_set_ios,
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// .init_card = mshci_cnc1800l_init_card,
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};
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static int cnc1800lsd_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mshci_host *host = NULL;
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struct device *dev = &pdev->dev;
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struct cnc1800lsd_host *cardhost = NULL;
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int ret, irq;
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if (!np) {
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dev_err(&pdev->dev, "no DT node\n");
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return -ENODEV;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return -ENXIO;
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host = mshci_alloc_host(dev, sizeof(struct cnc1800lsd_host));
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if (!host) {
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ret = -ENOMEM;
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goto out;
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}
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cardhost = mshci_priv(host);
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cardhost->ctrl1 = ioremap(0xB2100140,4);
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if (IS_ERR(cardhost->ctrl1)) {
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ret = PTR_ERR(cardhost->ctrl1);
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goto out;
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}
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cardhost->ctrl2 = ioremap(0xB2110024,4);
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if (IS_ERR(cardhost->ctrl2)) {
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ret = PTR_ERR(cardhost->ctrl2);
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goto out;
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}
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cardhost->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(cardhost->base)) {
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ret = PTR_ERR(cardhost->base);
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goto out;
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}
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*cardhost->ctrl1 = 0xffffffff;
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*cardhost->ctrl2 = 0x1;
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mdelay(100);
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// In the original source, manipulate GPIO here in order to enable WLAN on TIGA_MINI platform.
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// But, I won't touch it :)
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cardhost->host = host;
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cardhost->pdev = pdev;
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platform_set_drvdata(pdev,host);
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cardhost->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(cardhost->clk)) {
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dev_err(&pdev->dev, "no clock associated\n");
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ret = -EINVAL;
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goto out;
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}
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clk_prepare_enable(cardhost->clk);
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host->ioaddr = cardhost->base;
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host->hw_name = "cavium-mshci";
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host->ops = &mshci_cnc1800l_ops;
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host->quirks = 0;
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host->irq = irq;
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host->mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED |
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MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ;
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host->quirks |= MSHCI_QUIRK_BROKEN_PRESENT_BIT | MSHCI_QUIRK_1BIT_INTERRUPT;
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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ret = mshci_add_host(host);
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if(ret){
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dev_err(dev, "mshci_add_host() failed\n");
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goto out;
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}
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return 0;
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out:
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return ret;
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}
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static int cnc1800lsd_remove(struct platform_device *pdev)
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{
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struct cnc1800lsd_host *pdata = pdev->dev.platform_data;
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struct mshci_host *host = platform_get_drvdata(pdev);
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mshci_remove_host(host, 1);
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pdata->ctrl2 = 0x0;
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return 0;
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}
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static const struct of_device_id cnc1800lsdio_dt_ids[] = {
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{ .compatible = "cavium,cnc1800l-sdio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cnc1800lsdio_dt_ids);
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static struct platform_driver cnc1800lsd_driver = {
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.probe = cnc1800lsd_probe,
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.remove = cnc1800lsd_remove,
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.driver = {
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.name = DRIVER_NAME,
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = cnc1800lsdio_dt_ids,
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},
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};
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module_platform_driver(cnc1800lsd_driver);
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MODULE_DESCRIPTION("Cavium Celestial MSHCI glue");
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MODULE_AUTHOR("Scott Shu <sshu@caviumnetworks.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:cnc1800l-mshci");
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1742
drivers/mmc/host/mshci.c
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1742
drivers/mmc/host/mshci.c
Normal file
File diff suppressed because it is too large
Load Diff
296
drivers/mmc/host/mshci.h
Normal file
296
drivers/mmc/host/mshci.h
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@ -0,0 +1,296 @@
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/*
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* linux/drivers/mmc/host/mshci.h
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*
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* Mobile Storage Host Controller Interface driver
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Based on linux/drivers/mmc/host/sdhci.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef __MSHCI_H
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#define __MSHCI_H
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#include <linux/scatterlist.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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/* MSHC Internal Registers */
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#define MSHCI_CTRL 0x00 /* Control */
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#define MSHCI_PWREN 0x04 /* Power-enable */
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#define MSHCI_CLKDIV 0x08 /* Clock divider */
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#define MSHCI_CLKSRC 0x0C /* Clock source */
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#define MSHCI_CLKENA 0x10 /* Clock enable */
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#define MSHCI_TMOUT 0x14 /* Timeout */
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#define MSHCI_CTYPE 0x18 /* Card type */
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#define MSHCI_BLKSIZ 0x1C /* Block Size */
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#define MSHCI_BYTCNT 0x20 /* Byte count */
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#define MSHCI_INTMSK 0x24 /* Interrupt Mask */
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#define MSHCI_CMDARG 0x28 /* Command Argument */
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#define MSHCI_CMD 0x2C /* Command */
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#define MSHCI_RESP0 0x30 /* Response 0 */
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#define MSHCI_RESP1 0x34 /* Response 1 */
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#define MSHCI_RESP2 0x38 /* Response 2 */
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#define MSHCI_RESP3 0x3C /* Response 3 */
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#define MSHCI_MINTSTS 0x40 /* Masked interrupt status */
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#define MSHCI_RINTSTS 0x44 /* Raw interrupt status */
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#define MSHCI_STATUS 0x48 /* Status */
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#define MSHCI_FIFOTH 0x4C /* FIFO threshold */
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#define MSHCI_CDETECT 0x50 /* Card detect */
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#define MSHCI_WRTPRT 0x54 /* Write protect */
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#define MSHCI_GPIO 0x58 /* General Purpose IO */
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#define MSHCI_TCBCNT 0x5C /* Transferred CIU byte count */
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#define MSHCI_TBBCNT 0x60 /* Transferred host/DMA to/from byte count */
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#define MSHCI_DEBNCE 0x64 /* Card detect debounce */
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#define MSHCI_USRID 0x68 /* User ID */
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#define MSHCI_VERID 0x6C /* Version ID */
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#define MSHCI_HCON 0x70 /* Hardware Configuration */
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#define MSHCI_UHS_REG 0x74 /* UHS and DDR setting */
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#define MSHCI_BMOD 0x80 /* Bus mode register */
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#define MSHCI_PLDMND 0x84 /* Poll demand */
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#define MSHCI_DBADDR 0x88 /* Descriptor list base address */
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#define MSHCI_IDSTS 0x8C /* Internal DMAC status */
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#define MSHCI_IDINTEN 0x90 /* Internal DMAC interrupt enable */
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#define MSHCI_DSCADDR 0x94 /* Current host descriptor address */
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#define MSHCI_BUFADDR 0x98 /* Current host buffer address */
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#define MSHCI_CLKSEL 0x9C
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#define MSHCI_WAKEUPCON 0xA0 /* Wakeup control register */
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#define MSHCI_CLOCKCON 0xA4 /* Clock (delay) control register */
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#define MSHCI_FIFODAT 0x100 /* FIFO data read write */
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/* Control Register MSHCI_CTRL(offset 0x00) */
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#define CTRL_RESET (0x1 << 0) /* Reset DWC_mobile_storage controller */
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#define FIFO_RESET (0x1 << 1) /* Reset FIFO */
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#define DMA_RESET (0x1 << 2) /* Reset DMA interface */
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#define INT_ENABLE (0x1 << 4) /* Global interrupt enable/disable bit */
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#define DMA_ENABLE (0x1 << 5) /* DMA transfer mode enable/disable bit */
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#define ENABLE_IDMAC (0x1 << 25)
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/* Clock Enable Register MSHCI_CLKENA(offset 0x10) */
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#define CLK_ENABLE (0x1 << 0)
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#define CLK_DISABLE (0x0 << 0)
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/* Interrupt Mask Register MSHCI_INTMSK(offset 0x24) */
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#define SDIO_INT_ENABLE (0x1 << 16)
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/* Interrupt bits */
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#define INTMSK_ALL 0xFFFFFFFF
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#define INTMSK_CDETECT (0x1 << 0)
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#define INTMSK_RE (0x1 << 1)
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#define INTMSK_CDONE (0x1 << 2)
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#define INTMSK_DTO (0x1 << 3)
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#define INTMSK_TXDR (0x1 << 4)
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#define INTMSK_RXDR (0x1 << 5)
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#define INTMSK_RCRC (0x1 << 6)
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#define INTMSK_DCRC (0x1 << 7)
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#define INTMSK_RTO (0x1 << 8)
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#define INTMSK_DRTO (0x1 << 9)
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#define INTMSK_HTO (0x1 << 10)
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#define INTMSK_FRUN (0x1 << 11)
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#define INTMSK_HLE (0x1 << 12)
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#define INTMSK_SBE (0x1 << 13)
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#define INTMSK_ACD (0x1 << 14)
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#define INTMSK_EBE (0x1 << 15)
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#define INTMSK_DMA (INTMSK_ACD | INTMSK_RXDR | INTMSK_TXDR)
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#define INT_SRC_IDMAC (0x0)
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#define INT_SRC_MINT (0x1)
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/* Command Register MSHCI_CMD(offset 0x2C) */
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#define CMD_RESP_EXP_BIT (0x1 << 6)
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#define CMD_RESP_LENGTH_BIT (0x1 << 7)
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#define CMD_CHECK_CRC_BIT (0x1 << 8)
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#define CMD_DATA_EXP_BIT (0x1 << 9)
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#define CMD_RW_BIT (0x1 << 10)
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#define CMD_TRANSMODE_BIT (0x1 << 11)
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#define CMD_WAIT_PRV_DAT_BIT (0x1 << 13)
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#define CMD_SEND_CLK_ONLY (0x1 << 21)
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#define CMD_STRT_BIT (0x1 << 31)
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#define CMD_ONLY_CLK (CMD_STRT_BIT | CMD_SEND_CLK_ONLY | \
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CMD_WAIT_PRV_DAT_BIT)
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/* Raw Interrupt Register MSHCI_RINTSTS(offset 0x44) */
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#define DATA_ERR (INTMSK_EBE | INTMSK_SBE | INTMSK_HLE | \
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INTMSK_FRUN | INTMSK_EBE | INTMSK_DCRC)
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#define DATA_TOUT (INTMSK_HTO | INTMSK_DRTO)
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#define DATA_STATUS (DATA_ERR | DATA_TOUT | INTMSK_RXDR | \
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INTMSK_TXDR | INTMSK_DTO)
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#define CMD_STATUS (INTMSK_RTO | INTMSK_RCRC | INTMSK_CDONE | \
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INTMSK_RE)
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/* Status Register MSHCI_STATUS(offset 0x48) */
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#define FIFO_COUNT (0x1FFF << 17)
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#define FIFO_WIDTH (0x4)
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/* FIFO Threshold Watermark Register MSHCI_FIFOTH(offset 0x4C) */
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#define TX_WMARK (0xFFF << 0)
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#define RX_WMARK (0xFFF << 16)
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#define MSIZE_MASK (0x7 << 28)
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/* DW DMA Mutiple Transaction Size */
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#define MSIZE_8 (2 << 28)
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/*
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* Card Detect Register MSHCI_CDETECT(offset 0x50)
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* It assumes there is only one SD slot
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*/
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#define CARD_PRESENT (0x1 << 0)
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/*
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* Write Protect Register MSHCI_WRTPRT(offset 0x54)
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* It assumes there is only one SD slot
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*/
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#define WRTPRT_ON (0x1 << 0)
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/* Bus Mode Register MSHCI_BMOD(offset 0x80) */
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#define BMOD_IDMAC_RESET (0x1 << 1)
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#define BMOD_IDMAC_FB (0x1 << 1)
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#define BMOD_IDMAC_ENABLE (0x1 << 7)
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/* Hardware Configuration Register MSHCI_IDSTS(offset 0x8c) */
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#define IDSTS_CES (0x1 << 5)
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#define IDSTS_DU (0x1 << 4)
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#define IDSTS_FBE (0x1 << 2)
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struct mshci_ops;
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struct mshci_idmac {
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u32 des0;
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u32 des1;
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u32 des2;
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u32 des3;
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#define MSHCI_IDMAC_OWN (1 << 31)
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#define MSHCI_IDMAC_CH (1 << 4)
|
||||
#define MSHCI_IDMAC_FS (1 << 3)
|
||||
#define MSHCI_IDMAC_LD (1 << 2)
|
||||
#define INTMSK_IDMAC_ERROR (0x214)
|
||||
};
|
||||
|
||||
struct mshci_host {
|
||||
/* Data set by hardware interface driver */
|
||||
const char *hw_name; /* Hardware bus name */
|
||||
|
||||
unsigned int quirks; /* Deviations from spec. */
|
||||
|
||||
/* Controller has no write-protect pin connected with SD card */
|
||||
|
||||
#define MSHCI_QUIRK_NO_WP_BIT (1 << 0)
|
||||
#define MSHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 1)
|
||||
#define MSHCI_QUIRK_ALWAYS_WRITABLE (1 << 2)
|
||||
#define MSHCI_QUIRK_BROKEN_PRESENT_BIT (1 << 3)
|
||||
#define MSHCI_QUIRK_1BIT_INTERRUPT (1 << 4)
|
||||
|
||||
int irq; /* Device IRQ */
|
||||
void __iomem *ioaddr; /* Mapped address */
|
||||
|
||||
const struct mshci_ops *ops; /* Low level hw interface */
|
||||
|
||||
/* Internal data */
|
||||
struct mmc_host *mmc; /* MMC structure */
|
||||
u64 dma_mask; /* custom DMA mask */
|
||||
|
||||
spinlock_t lock; /* Mutex */
|
||||
|
||||
int flags; /* Host attributes */
|
||||
#define MSHCI_USE_IDMA (1 << 1) /* Host is ADMA capable */
|
||||
#define MSHCI_REQ_USE_DMA (1 << 2) /* Use DMA for this req. */
|
||||
#define MSHCI_DEVICE_DEAD (1 << 3) /* Device unresponsive */
|
||||
#define MSHCI_IN_4BIT_MODE (1 << 4) /* bus is in 4-bit mode */
|
||||
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
|
||||
unsigned int max_clk; /* Max possible freq (MHz) */
|
||||
unsigned int timeout_clk; /* Timeout freq (KHz) */
|
||||
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
unsigned int clock_to_restore; /* Saved clock for dynamic clock gating (MHz) */
|
||||
u8 pwr; /* Current voltage */
|
||||
|
||||
struct mmc_request *mrq; /* Current request */
|
||||
struct mmc_command *cmd; /* Current command */
|
||||
struct mmc_data *data; /* Current data request */
|
||||
unsigned int data_early:1; /* Data finished before cmd */
|
||||
|
||||
struct sg_mapping_iter sg_miter; /* SG state for PIO */
|
||||
unsigned int blocks; /* remaining PIO blocks */
|
||||
|
||||
int sg_count; /* Mapped sg entries */
|
||||
|
||||
u8 *idma_desc; /* ADMA descriptor table */
|
||||
u8 *align_buffer; /* Bounce buffer */
|
||||
|
||||
dma_addr_t idma_addr; /* Mapped ADMA descr. table */
|
||||
dma_addr_t align_addr; /* Mapped bounce buffer */
|
||||
|
||||
struct tasklet_struct card_tasklet; /* Tasklet structures */
|
||||
struct tasklet_struct finish_tasklet;
|
||||
|
||||
struct timer_list timer; /* Timer for timeouts */
|
||||
struct timer_list clock_timer; /* Timer for clock gating */
|
||||
|
||||
u32 fifo_depth;
|
||||
u32 fifo_threshold;
|
||||
u32 data_transfered;
|
||||
u32 error_state;
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
};
|
||||
|
||||
struct mshci_ops {
|
||||
void (*set_clock)(struct mshci_host *host, unsigned int clock);
|
||||
|
||||
int (*enable_dma)(struct mshci_host *host);
|
||||
unsigned int (*get_max_clock)(struct mshci_host *host);
|
||||
unsigned int (*get_min_clock)(struct mshci_host *host);
|
||||
unsigned int (*get_timeout_clock)(struct mshci_host *host);
|
||||
void (*set_ios)(struct mshci_host *host, struct mmc_ios *ios);
|
||||
int (*get_ro)(struct mmc_host *mmc);
|
||||
void (*init_issue_cmd)(struct mshci_host *host);
|
||||
void (*init_card)(struct mshci_host *host);
|
||||
};
|
||||
|
||||
static inline void mshci_writel(struct mshci_host *host, u32 val, int reg)
|
||||
{
|
||||
writel(val, host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline u32 mshci_readl(struct mshci_host *host, int reg)
|
||||
{
|
||||
return readl(host->ioaddr + reg);
|
||||
}
|
||||
|
||||
extern struct mshci_host *mshci_alloc_host(struct device *dev,
|
||||
size_t priv_size);
|
||||
extern void mshci_free_host(struct mshci_host *host);
|
||||
|
||||
static inline void *mshci_priv(struct mshci_host *host)
|
||||
{
|
||||
return (void *)host->private;
|
||||
}
|
||||
|
||||
extern int mshci_add_host(struct mshci_host *host);
|
||||
extern void mshci_remove_host(struct mshci_host *host, int dead);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern int mshci_suspend_host(struct mshci_host *host, pm_message_t state);
|
||||
extern int mshci_resume_host(struct mshci_host *host);
|
||||
#endif
|
||||
|
||||
#endif /* __MSHCI_H */
|
||||
Loading…
x
Reference in New Issue
Block a user