135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
/****************************************************************************
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* Copyright (C) 2008-2010 Celestial Semiconductor Inc.
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* All rights reserved
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*
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* [RELEASE HISTORY]
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* VERSION DATE AUTHOR DESCRIPTION
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* 0.1 10-03-10 Jia Ma Original
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****************************************************************************
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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// #define CLOCK_ID_BASE (CLOCK_REG_BASE+(0<<2))
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// #define CLOCK_PLL_BASE (CLOCK_REG_BASE+(0x40<<2))
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// #define CLOCK_MUX_BASE (CLOCK_REG_BASE+(0x50<<2))
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// #define CLOCK_RESET_BASE (CLOCK_REG_BASE+(0x80<<2))
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// #define CLOCK_ID_LO (CLOCK_ID_BASE+(0<<2))
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// #define CLOCK_ID_HI (CLOCK_ID_BASE+(1<<2))
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// #define CLOCK_PLL_DDR_DIV (CLOCK_PLL_BASE+(0<<2))
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// #define CLOCK_PLL_AVS_DIV (CLOCK_PLL_BASE+(1<<2))
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// #define CLOCK_PLL_TVE_DIV (CLOCK_PLL_BASE+(2<<2))
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// #define CLOCK_AUD_HPD (CLOCK_PLL_BASE+(3<<2))
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// #define CLOCK_AUD_FREQ (CLOCK_PLL_BASE+(6<<2))
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// #define CLOCK_AUD_JITTER (CLOCK_PLL_BASE+(7<<2))
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// #define CLOCK_CLK_GEN_DIV (CLOCK_PLL_BASE+(8<<2))
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// #define CLOCK_PLL_CLK_EN (CLOCK_MUX_BASE+(0<<2))
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// #define CLOCK_TVE_SEL (CLOCK_MUX_BASE+(1<<2))
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// #define CLOCK_TVE_DIV_N (CLOCK_MUX_BASE+(2<<2))
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// #define CLOCK_SOFT_RESET (CLOCK_RESET_BASE+(0<<2))
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// #define CLOCK_CLK_RESET (CLOCK_RESET_BASE+(1<<2))
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// #define CLOCK_PLL_SLEEP_N (CLOCK_RESET_BASE+(3<<2))
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// #define CLOCK_DAC_POWER_DOWN (CLOCK_RESET_BASE+(4<<2))
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// #define CLOCK_XPORT_CLK_SEL (CLOCK_RESET_BASE+(5<<2))
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// #define CLOCK_USB_ULPI_BYPASS (CLOCK_RESET_BASE+(6<<2))
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// #define CLOCK_AUD_POWER_ON (CLOCK_RESET_BASE+(7<<2))
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// #define CLOCK_LOW_POWER_CTL (CLOCK_PLL_BASE+(0x10<<2))
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#define CLOCK_ID_BASE (0<<2)
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#define CLOCK_PLL_BASE (0x40<<2)
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#define CLOCK_MUX_BASE (0x50<<2)
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#define CLOCK_RESET_BASE (0x80<<2)
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#define CLOCK_ID_LO (CLOCK_ID_BASE+(0<<2))
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#define CLOCK_ID_HI (CLOCK_ID_BASE+(1<<2))
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#define CLOCK_PLL_DDR_DIV (CLOCK_PLL_BASE+(0<<2))
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#define CLOCK_PLL_AVS_DIV (CLOCK_PLL_BASE+(1<<2))
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#define CLOCK_PLL_TVE_DIV (CLOCK_PLL_BASE+(2<<2))
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#define CLOCK_AUD_HPD (CLOCK_PLL_BASE+(3<<2))
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#define CLOCK_AUD_FREQ (CLOCK_PLL_BASE+(6<<2))
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#define CLOCK_AUD_JITTER (CLOCK_PLL_BASE+(7<<2))
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#define CLOCK_CLK_GEN_DIV (CLOCK_PLL_BASE+(8<<2))
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#define CLOCK_PLL_CLK_EN (CLOCK_MUX_BASE+(0<<2))
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#define CLOCK_TVE_SEL (CLOCK_MUX_BASE+(1<<2))
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#define CLOCK_TVE_DIV_N (CLOCK_MUX_BASE+(2<<2))
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#define CLOCK_SOFT_RESET (CLOCK_RESET_BASE+(0<<2))
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#define CLOCK_CLK_RESET (CLOCK_RESET_BASE+(1<<2))
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#define CLOCK_PLL_SLEEP_N (CLOCK_RESET_BASE+(3<<2))
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#define CLOCK_DAC_POWER_DOWN (CLOCK_RESET_BASE+(4<<2))
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#define CLOCK_XPORT_CLK_SEL (CLOCK_RESET_BASE+(5<<2))
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#define CLOCK_USB_ULPI_BYPASS (CLOCK_RESET_BASE+(6<<2))
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#define CLOCK_AUD_POWER_ON (CLOCK_RESET_BASE+(7<<2))
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#define CLOCK_LOW_POWER_CTL (CLOCK_PLL_BASE+(0x10<<2))
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static void __iomem *cnc1800l_clockctrl_base;
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#define cnc_clk_read(a) readl(cnc1800l_clockctrl_base+((a)&0xfff))
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#define cnc_clk_write(a,v) writel(v,cnc1800l_clockctrl_base+((a)&0xfff))
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//mode 0:reset
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// 1:set
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void cnc1800l_clock_usb_reset(int mode){
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unsigned int val;
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if(mode == 0){
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val = cnc_clk_read(CLOCK_SOFT_RESET);
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cnc_clk_write(CLOCK_SOFT_RESET, val&(~(0x1<<4)));
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}else{
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val = cnc_clk_read(CLOCK_SOFT_RESET);
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cnc_clk_write(CLOCK_SOFT_RESET, val|(0x1<<4));
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}
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}
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void cnc1800l_clock_usb1phy_bypassenable(void)
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{
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unsigned int val;
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val = cnc_clk_read(CLOCK_USB_ULPI_BYPASS);
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cnc_clk_write(CLOCK_USB_ULPI_BYPASS, val|0x3);
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}
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void cnc1800l_clock_usb1phy_bypassdisable(void)
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{
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unsigned int reg_val;
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reg_val = cnc_clk_read(CLOCK_USB_ULPI_BYPASS);
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cnc_clk_write(CLOCK_USB_ULPI_BYPASS, reg_val|0x1);
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}
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static void __init cnc1800l_clock_init(struct device_node *np)
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{
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cnc1800l_clockctrl_base = of_io_request_and_map(np, 0, np->name);
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if (IS_ERR(cnc1800l_clockctrl_base)){
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panic("%pOFn: unable to map resource", np);
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goto fail;
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}
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printk("cnc1800l clockctrl init");
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return;
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fail:
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iounmap(cnc1800l_clockctrl_base);
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}
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EXPORT_SYMBOL(cnc1800l_clock_usb_reset);
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EXPORT_SYMBOL(cnc1800l_clock_usb1phy_bypassenable);
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EXPORT_SYMBOL(cnc1800l_clock_usb1phy_bypassdisable);
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CLK_OF_DECLARE(cnc1800l_clock, "cavium,cnc1800l-clockctrl",
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cnc1800l_clock_init);
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