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The MAC hardware supports receiving two types of pause frames from link partner. One is a pause frame with a destination address of 01:80:C2:00:00:01. The other is a pause frame whose destination address is the address of the hibmcge driver. 01:80:C2:00:00:01 is supported by default. In .ndo_set_mac_address(), the hibmcge driver calls .hbg_hw_set_rx_pause_mac_addr() to set its mac address as the destination address of the rx puase frame. Therefore, pause frames with two types of MAC addresses can be received. Currently, the rx pause addr does not restored after reset. As a result, pause frames whose destination address is the hibmcge driver address cannot be correctly received. This patch restores the configuration by calling .hbg_hw_set_rx_pause_mac_addr() after reset is complete. Fixes: 3f5a61f6d504 ("net: hibmcge: Add reset supported in this module") Signed-off-by: Jijie Shao <shaojijie@huawei.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20250410021327.590362-7-shaojijie@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
196 lines
4.4 KiB
C
196 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright (c) 2024 Hisilicon Limited.
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <linux/rtnetlink.h>
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#include "hbg_common.h"
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#include "hbg_err.h"
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#include "hbg_hw.h"
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static void hbg_restore_mac_table(struct hbg_priv *priv)
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{
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struct hbg_mac_filter *filter = &priv->filter;
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u64 addr;
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u32 i;
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for (i = 0; i < filter->table_max_len; i++)
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if (!is_zero_ether_addr(filter->mac_table[i].addr)) {
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addr = ether_addr_to_u64(filter->mac_table[i].addr);
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hbg_hw_set_uc_addr(priv, addr, i);
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}
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hbg_hw_set_mac_filter_enable(priv, priv->filter.enabled);
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}
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static void hbg_restore_user_def_settings(struct hbg_priv *priv)
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{
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/* The index of host mac is always 0. */
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u64 rx_pause_addr = ether_addr_to_u64(priv->filter.mac_table[0].addr);
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struct ethtool_pauseparam *pause_param = &priv->user_def.pause_param;
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hbg_restore_mac_table(priv);
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hbg_hw_set_mtu(priv, priv->netdev->mtu);
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hbg_hw_set_pause_enable(priv, pause_param->tx_pause,
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pause_param->rx_pause);
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hbg_hw_set_rx_pause_mac_addr(priv, rx_pause_addr);
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}
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int hbg_rebuild(struct hbg_priv *priv)
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{
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int ret;
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ret = hbg_hw_init(priv);
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if (ret)
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return ret;
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hbg_restore_user_def_settings(priv);
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return 0;
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}
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static int hbg_reset_prepare(struct hbg_priv *priv, enum hbg_reset_type type)
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{
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int ret;
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ASSERT_RTNL();
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if (netif_running(priv->netdev)) {
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dev_warn(&priv->pdev->dev,
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"failed to reset because port is up\n");
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return -EBUSY;
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}
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priv->reset_type = type;
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set_bit(HBG_NIC_STATE_RESETTING, &priv->state);
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clear_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
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ret = hbg_hw_event_notify(priv, HBG_HW_EVENT_RESET);
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if (ret) {
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set_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
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clear_bit(HBG_NIC_STATE_RESETTING, &priv->state);
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}
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return ret;
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}
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static int hbg_reset_done(struct hbg_priv *priv, enum hbg_reset_type type)
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{
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int ret;
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if (!test_bit(HBG_NIC_STATE_RESETTING, &priv->state) ||
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type != priv->reset_type)
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return 0;
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ASSERT_RTNL();
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clear_bit(HBG_NIC_STATE_RESETTING, &priv->state);
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ret = hbg_rebuild(priv);
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if (ret) {
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set_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
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dev_err(&priv->pdev->dev, "failed to rebuild after reset\n");
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return ret;
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}
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dev_info(&priv->pdev->dev, "reset done\n");
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return ret;
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}
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/* must be protected by rtnl lock */
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int hbg_reset(struct hbg_priv *priv)
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{
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int ret;
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ASSERT_RTNL();
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ret = hbg_reset_prepare(priv, HBG_RESET_TYPE_FUNCTION);
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if (ret)
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return ret;
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return hbg_reset_done(priv, HBG_RESET_TYPE_FUNCTION);
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}
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void hbg_err_reset(struct hbg_priv *priv)
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{
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bool running;
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rtnl_lock();
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running = netif_running(priv->netdev);
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if (running)
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dev_close(priv->netdev);
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hbg_reset(priv);
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/* in hbg_pci_err_detected(), we will detach first,
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* so we need to attach before open
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*/
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if (!netif_device_present(priv->netdev))
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netif_device_attach(priv->netdev);
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if (running)
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dev_open(priv->netdev, NULL);
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rtnl_unlock();
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}
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static pci_ers_result_t hbg_pci_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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struct net_device *netdev = pci_get_drvdata(pdev);
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netif_device_detach(netdev);
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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pci_disable_device(pdev);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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static pci_ers_result_t hbg_pci_err_slot_reset(struct pci_dev *pdev)
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{
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struct net_device *netdev = pci_get_drvdata(pdev);
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struct hbg_priv *priv = netdev_priv(netdev);
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if (pci_enable_device(pdev)) {
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dev_err(&pdev->dev,
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"failed to re-enable PCI device after reset\n");
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return PCI_ERS_RESULT_DISCONNECT;
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}
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pci_set_master(pdev);
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pci_restore_state(pdev);
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pci_save_state(pdev);
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hbg_err_reset(priv);
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netif_device_attach(netdev);
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return PCI_ERS_RESULT_RECOVERED;
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}
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static void hbg_pci_err_reset_prepare(struct pci_dev *pdev)
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{
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struct net_device *netdev = pci_get_drvdata(pdev);
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struct hbg_priv *priv = netdev_priv(netdev);
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rtnl_lock();
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hbg_reset_prepare(priv, HBG_RESET_TYPE_FLR);
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}
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static void hbg_pci_err_reset_done(struct pci_dev *pdev)
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{
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struct net_device *netdev = pci_get_drvdata(pdev);
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struct hbg_priv *priv = netdev_priv(netdev);
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hbg_reset_done(priv, HBG_RESET_TYPE_FLR);
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rtnl_unlock();
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}
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static const struct pci_error_handlers hbg_pci_err_handler = {
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.error_detected = hbg_pci_err_detected,
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.slot_reset = hbg_pci_err_slot_reset,
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.reset_prepare = hbg_pci_err_reset_prepare,
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.reset_done = hbg_pci_err_reset_done,
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};
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void hbg_set_pci_err_handler(struct pci_driver *pdrv)
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{
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pdrv->err_handler = &hbg_pci_err_handler;
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}
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