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In v2 of rqspinlock [0], we fixed potential problems with WFE usage in arm64 to fallback to a version copied from Ankur's series [1]. This logic was moved into arch-specific headers in v3 [2]. However, we missed using the arch-provided res_smp_cond_load_acquire in commit ebababcd0372 ("rqspinlock: Hardcode cond_acquire loops for arm64") due to a rebasing mistake between v2 and v3 of the rqspinlock series. Fix the typo to fallback to the arm64 definition as we did in v2. [0]: https://lore.kernel.org/bpf/20250206105435.2159977-18-memxor@gmail.com [1]: https://lore.kernel.org/lkml/20250203214911.898276-1-ankur.a.arora@oracle.com [2]: https://lore.kernel.org/bpf/20250303152305.3195648-9-memxor@gmail.com Fixes: ebababcd0372 ("rqspinlock: Hardcode cond_acquire loops for arm64") Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Link: https://lore.kernel.org/r/20250410145512.1876745-1-memxor@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
738 lines
21 KiB
C
738 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Resilient Queued Spin Lock
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*
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* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
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* (C) Copyright 2013-2014,2018 Red Hat, Inc.
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* (C) Copyright 2015 Intel Corp.
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* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
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* (C) Copyright 2024-2025 Meta Platforms, Inc. and affiliates.
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*
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* Authors: Waiman Long <longman@redhat.com>
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* Peter Zijlstra <peterz@infradead.org>
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* Kumar Kartikeya Dwivedi <memxor@gmail.com>
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*/
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#include <linux/smp.h>
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#include <linux/bug.h>
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#include <linux/bpf.h>
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#include <linux/err.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/mutex.h>
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#include <linux/prefetch.h>
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#include <asm/byteorder.h>
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#ifdef CONFIG_QUEUED_SPINLOCKS
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#include <asm/qspinlock.h>
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#endif
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#include <trace/events/lock.h>
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#include <asm/rqspinlock.h>
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#include <linux/timekeeping.h>
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/*
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* Include queued spinlock definitions and statistics code
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*/
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#ifdef CONFIG_QUEUED_SPINLOCKS
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#include "../locking/qspinlock.h"
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#include "../locking/lock_events.h"
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#include "rqspinlock.h"
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#include "../locking/mcs_spinlock.h"
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#endif
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/*
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* The basic principle of a queue-based spinlock can best be understood
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* by studying a classic queue-based spinlock implementation called the
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* MCS lock. A copy of the original MCS lock paper ("Algorithms for Scalable
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* Synchronization on Shared-Memory Multiprocessors by Mellor-Crummey and
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* Scott") is available at
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*
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* https://bugzilla.kernel.org/show_bug.cgi?id=206115
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*
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* This queued spinlock implementation is based on the MCS lock, however to
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* make it fit the 4 bytes we assume spinlock_t to be, and preserve its
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* existing API, we must modify it somehow.
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*
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* In particular; where the traditional MCS lock consists of a tail pointer
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* (8 bytes) and needs the next pointer (another 8 bytes) of its own node to
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* unlock the next pending (next->locked), we compress both these: {tail,
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* next->locked} into a single u32 value.
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*
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* Since a spinlock disables recursion of its own context and there is a limit
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* to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there
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* are at most 4 nesting levels, it can be encoded by a 2-bit number. Now
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* we can encode the tail by combining the 2-bit nesting level with the cpu
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* number. With one byte for the lock value and 3 bytes for the tail, only a
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* 32-bit word is now needed. Even though we only need 1 bit for the lock,
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* we extend it to a full byte to achieve better performance for architectures
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* that support atomic byte write.
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*
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* We also change the first spinner to spin on the lock bit instead of its
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* node; whereby avoiding the need to carry a node from lock to unlock, and
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* preserving existing lock API. This also makes the unlock code simpler and
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* faster.
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*
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* N.B. The current implementation only supports architectures that allow
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* atomic operations on smaller 8-bit and 16-bit data types.
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*
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*/
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struct rqspinlock_timeout {
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u64 timeout_end;
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u64 duration;
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u64 cur;
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u16 spin;
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};
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#define RES_TIMEOUT_VAL 2
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DEFINE_PER_CPU_ALIGNED(struct rqspinlock_held, rqspinlock_held_locks);
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EXPORT_SYMBOL_GPL(rqspinlock_held_locks);
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static bool is_lock_released(rqspinlock_t *lock, u32 mask, struct rqspinlock_timeout *ts)
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{
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if (!(atomic_read_acquire(&lock->val) & (mask)))
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return true;
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return false;
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}
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static noinline int check_deadlock_AA(rqspinlock_t *lock, u32 mask,
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struct rqspinlock_timeout *ts)
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{
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struct rqspinlock_held *rqh = this_cpu_ptr(&rqspinlock_held_locks);
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int cnt = min(RES_NR_HELD, rqh->cnt);
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/*
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* Return an error if we hold the lock we are attempting to acquire.
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* We'll iterate over max 32 locks; no need to do is_lock_released.
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*/
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for (int i = 0; i < cnt - 1; i++) {
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if (rqh->locks[i] == lock)
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return -EDEADLK;
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}
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return 0;
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}
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/*
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* This focuses on the most common case of ABBA deadlocks (or ABBA involving
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* more locks, which reduce to ABBA). This is not exhaustive, and we rely on
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* timeouts as the final line of defense.
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*/
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static noinline int check_deadlock_ABBA(rqspinlock_t *lock, u32 mask,
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struct rqspinlock_timeout *ts)
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{
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struct rqspinlock_held *rqh = this_cpu_ptr(&rqspinlock_held_locks);
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int rqh_cnt = min(RES_NR_HELD, rqh->cnt);
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void *remote_lock;
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int cpu;
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/*
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* Find the CPU holding the lock that we want to acquire. If there is a
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* deadlock scenario, we will read a stable set on the remote CPU and
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* find the target. This would be a constant time operation instead of
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* O(NR_CPUS) if we could determine the owning CPU from a lock value, but
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* that requires increasing the size of the lock word.
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*/
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for_each_possible_cpu(cpu) {
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struct rqspinlock_held *rqh_cpu = per_cpu_ptr(&rqspinlock_held_locks, cpu);
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int real_cnt = READ_ONCE(rqh_cpu->cnt);
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int cnt = min(RES_NR_HELD, real_cnt);
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/*
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* Let's ensure to break out of this loop if the lock is available for
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* us to potentially acquire.
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*/
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if (is_lock_released(lock, mask, ts))
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return 0;
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/*
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* Skip ourselves, and CPUs whose count is less than 2, as they need at
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* least one held lock and one acquisition attempt (reflected as top
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* most entry) to participate in an ABBA deadlock.
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*
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* If cnt is more than RES_NR_HELD, it means the current lock being
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* acquired won't appear in the table, and other locks in the table are
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* already held, so we can't determine ABBA.
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*/
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if (cpu == smp_processor_id() || real_cnt < 2 || real_cnt > RES_NR_HELD)
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continue;
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/*
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* Obtain the entry at the top, this corresponds to the lock the
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* remote CPU is attempting to acquire in a deadlock situation,
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* and would be one of the locks we hold on the current CPU.
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*/
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remote_lock = READ_ONCE(rqh_cpu->locks[cnt - 1]);
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/*
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* If it is NULL, we've raced and cannot determine a deadlock
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* conclusively, skip this CPU.
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*/
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if (!remote_lock)
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continue;
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/*
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* Find if the lock we're attempting to acquire is held by this CPU.
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* Don't consider the topmost entry, as that must be the latest lock
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* being held or acquired. For a deadlock, the target CPU must also
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* attempt to acquire a lock we hold, so for this search only 'cnt - 1'
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* entries are important.
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*/
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for (int i = 0; i < cnt - 1; i++) {
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if (READ_ONCE(rqh_cpu->locks[i]) != lock)
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continue;
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/*
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* We found our lock as held on the remote CPU. Is the
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* acquisition attempt on the remote CPU for a lock held
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* by us? If so, we have a deadlock situation, and need
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* to recover.
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*/
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for (int i = 0; i < rqh_cnt - 1; i++) {
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if (rqh->locks[i] == remote_lock)
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return -EDEADLK;
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}
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/*
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* Inconclusive; retry again later.
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*/
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return 0;
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}
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}
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return 0;
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}
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static noinline int check_deadlock(rqspinlock_t *lock, u32 mask,
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struct rqspinlock_timeout *ts)
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{
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int ret;
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ret = check_deadlock_AA(lock, mask, ts);
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if (ret)
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return ret;
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ret = check_deadlock_ABBA(lock, mask, ts);
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if (ret)
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return ret;
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return 0;
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}
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static noinline int check_timeout(rqspinlock_t *lock, u32 mask,
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struct rqspinlock_timeout *ts)
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{
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u64 time = ktime_get_mono_fast_ns();
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u64 prev = ts->cur;
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if (!ts->timeout_end) {
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ts->cur = time;
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ts->timeout_end = time + ts->duration;
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return 0;
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}
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if (time > ts->timeout_end)
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return -ETIMEDOUT;
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/*
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* A millisecond interval passed from last time? Trigger deadlock
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* checks.
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*/
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if (prev + NSEC_PER_MSEC < time) {
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ts->cur = time;
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return check_deadlock(lock, mask, ts);
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}
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return 0;
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}
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/*
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* Do not amortize with spins when res_smp_cond_load_acquire is defined,
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* as the macro does internal amortization for us.
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*/
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#ifndef res_smp_cond_load_acquire
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#define RES_CHECK_TIMEOUT(ts, ret, mask) \
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({ \
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if (!(ts).spin++) \
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(ret) = check_timeout((lock), (mask), &(ts)); \
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(ret); \
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})
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#else
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#define RES_CHECK_TIMEOUT(ts, ret, mask) \
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({ (ret) = check_timeout((lock), (mask), &(ts)); })
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#endif
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/*
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* Initialize the 'spin' member.
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* Set spin member to 0 to trigger AA/ABBA checks immediately.
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*/
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#define RES_INIT_TIMEOUT(ts) ({ (ts).spin = 0; })
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/*
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* We only need to reset 'timeout_end', 'spin' will just wrap around as necessary.
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* Duration is defined for each spin attempt, so set it here.
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*/
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#define RES_RESET_TIMEOUT(ts, _duration) ({ (ts).timeout_end = 0; (ts).duration = _duration; })
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/*
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* Provide a test-and-set fallback for cases when queued spin lock support is
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* absent from the architecture.
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*/
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int __lockfunc resilient_tas_spin_lock(rqspinlock_t *lock)
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{
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struct rqspinlock_timeout ts;
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int val, ret = 0;
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RES_INIT_TIMEOUT(ts);
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grab_held_lock_entry(lock);
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/*
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* Since the waiting loop's time is dependent on the amount of
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* contention, a short timeout unlike rqspinlock waiting loops
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* isn't enough. Choose a second as the timeout value.
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*/
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RES_RESET_TIMEOUT(ts, NSEC_PER_SEC);
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retry:
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val = atomic_read(&lock->val);
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if (val || !atomic_try_cmpxchg(&lock->val, &val, 1)) {
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if (RES_CHECK_TIMEOUT(ts, ret, ~0u))
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goto out;
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cpu_relax();
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goto retry;
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}
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return 0;
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out:
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release_held_lock_entry();
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return ret;
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}
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EXPORT_SYMBOL_GPL(resilient_tas_spin_lock);
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#ifdef CONFIG_QUEUED_SPINLOCKS
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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* contexts: task, softirq, hardirq, nmi.
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*
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* Exactly fits one 64-byte cacheline on a 64-bit architecture.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct qnode, rqnodes[_Q_MAX_NODES]);
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#ifndef res_smp_cond_load_acquire
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#define res_smp_cond_load_acquire(v, c) smp_cond_load_acquire(v, c)
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#endif
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#define res_atomic_cond_read_acquire(v, c) res_smp_cond_load_acquire(&(v)->counter, (c))
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/**
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* resilient_queued_spin_lock_slowpath - acquire the queued spinlock
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* @lock: Pointer to queued spinlock structure
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* @val: Current value of the queued spinlock 32-bit word
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*
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* Return:
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* * 0 - Lock was acquired successfully.
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* * -EDEADLK - Lock acquisition failed because of AA/ABBA deadlock.
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* * -ETIMEDOUT - Lock acquisition failed because of timeout.
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*
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* (queue tail, pending bit, lock value)
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*
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* fast : slow : unlock
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* : :
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* uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0)
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* : | ^--------.------. / :
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* : v \ \ | :
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* pending : (0,1,1) +--> (0,1,0) \ | :
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* : | ^--' | | :
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* : v | | :
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* uncontended : (n,x,y) +--> (n,0,0) --' | :
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* queue : | ^--' | :
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* : v | :
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* contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' :
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* queue : ^--' :
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*/
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int __lockfunc resilient_queued_spin_lock_slowpath(rqspinlock_t *lock, u32 val)
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{
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struct mcs_spinlock *prev, *next, *node;
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struct rqspinlock_timeout ts;
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int idx, ret = 0;
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u32 old, tail;
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BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
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if (resilient_virt_spin_lock_enabled())
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return resilient_virt_spin_lock(lock);
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RES_INIT_TIMEOUT(ts);
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/*
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* Wait for in-progress pending->locked hand-overs with a bounded
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* number of spins so that we guarantee forward progress.
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*
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* 0,1,0 -> 0,0,1
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*/
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if (val == _Q_PENDING_VAL) {
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int cnt = _Q_PENDING_LOOPS;
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val = atomic_cond_read_relaxed(&lock->val,
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(VAL != _Q_PENDING_VAL) || !cnt--);
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}
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/*
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* If we observe any contention; queue.
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*/
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if (val & ~_Q_LOCKED_MASK)
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goto queue;
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/*
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* trylock || pending
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*
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* 0,0,* -> 0,1,* -> 0,0,1 pending, trylock
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*/
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val = queued_fetch_set_pending_acquire(lock);
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/*
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* If we observe contention, there is a concurrent locker.
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*
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* Undo and queue; our setting of PENDING might have made the
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* n,0,0 -> 0,0,0 transition fail and it will now be waiting
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* on @next to become !NULL.
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*/
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if (unlikely(val & ~_Q_LOCKED_MASK)) {
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/* Undo PENDING if we set it. */
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if (!(val & _Q_PENDING_MASK))
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clear_pending(lock);
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goto queue;
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}
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/*
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* Grab an entry in the held locks array, to enable deadlock detection.
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*/
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grab_held_lock_entry(lock);
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/*
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* We're pending, wait for the owner to go away.
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*
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* 0,1,1 -> *,1,0
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*
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* this wait loop must be a load-acquire such that we match the
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* store-release that clears the locked bit and create lock
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* sequentiality; this is because not all
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* clear_pending_set_locked() implementations imply full
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* barriers.
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*/
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if (val & _Q_LOCKED_MASK) {
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RES_RESET_TIMEOUT(ts, RES_DEF_TIMEOUT);
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res_smp_cond_load_acquire(&lock->locked, !VAL || RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_MASK));
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}
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if (ret) {
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/*
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* We waited for the locked bit to go back to 0, as the pending
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* waiter, but timed out. We need to clear the pending bit since
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* we own it. Once a stuck owner has been recovered, the lock
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* must be restored to a valid state, hence removing the pending
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* bit is necessary.
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*
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* *,1,* -> *,0,*
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*/
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clear_pending(lock);
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lockevent_inc(rqspinlock_lock_timeout);
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goto err_release_entry;
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}
|
|
|
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/*
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* take ownership and clear the pending bit.
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*
|
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* 0,1,0 -> 0,0,1
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*/
|
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clear_pending_set_locked(lock);
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lockevent_inc(lock_pending);
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return 0;
|
|
|
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/*
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* End of pending bit optimistic spinning and beginning of MCS
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* queuing.
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*/
|
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queue:
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lockevent_inc(lock_slowpath);
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/*
|
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* Grab deadlock detection entry for the queue path.
|
|
*/
|
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grab_held_lock_entry(lock);
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|
|
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node = this_cpu_ptr(&rqnodes[0].mcs);
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idx = node->count++;
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tail = encode_tail(smp_processor_id(), idx);
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|
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trace_contention_begin(lock, LCB_F_SPIN);
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|
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/*
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* 4 nodes are allocated based on the assumption that there will
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* not be nested NMIs taking spinlocks. That may not be true in
|
|
* some architectures even though the chance of needing more than
|
|
* 4 nodes will still be extremely unlikely. When that happens,
|
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* we fall back to spinning on the lock directly without using
|
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* any MCS node. This is not the most elegant solution, but is
|
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* simple enough.
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*/
|
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if (unlikely(idx >= _Q_MAX_NODES)) {
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lockevent_inc(lock_no_node);
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RES_RESET_TIMEOUT(ts, RES_DEF_TIMEOUT);
|
|
while (!queued_spin_trylock(lock)) {
|
|
if (RES_CHECK_TIMEOUT(ts, ret, ~0u)) {
|
|
lockevent_inc(rqspinlock_lock_timeout);
|
|
goto err_release_node;
|
|
}
|
|
cpu_relax();
|
|
}
|
|
goto release;
|
|
}
|
|
|
|
node = grab_mcs_node(node, idx);
|
|
|
|
/*
|
|
* Keep counts of non-zero index values:
|
|
*/
|
|
lockevent_cond_inc(lock_use_node2 + idx - 1, idx);
|
|
|
|
/*
|
|
* Ensure that we increment the head node->count before initialising
|
|
* the actual node. If the compiler is kind enough to reorder these
|
|
* stores, then an IRQ could overwrite our assignments.
|
|
*/
|
|
barrier();
|
|
|
|
node->locked = 0;
|
|
node->next = NULL;
|
|
|
|
/*
|
|
* We touched a (possibly) cold cacheline in the per-cpu queue node;
|
|
* attempt the trylock once more in the hope someone let go while we
|
|
* weren't watching.
|
|
*/
|
|
if (queued_spin_trylock(lock))
|
|
goto release;
|
|
|
|
/*
|
|
* Ensure that the initialisation of @node is complete before we
|
|
* publish the updated tail via xchg_tail() and potentially link
|
|
* @node into the waitqueue via WRITE_ONCE(prev->next, node) below.
|
|
*/
|
|
smp_wmb();
|
|
|
|
/*
|
|
* Publish the updated tail.
|
|
* We have already touched the queueing cacheline; don't bother with
|
|
* pending stuff.
|
|
*
|
|
* p,*,* -> n,*,*
|
|
*/
|
|
old = xchg_tail(lock, tail);
|
|
next = NULL;
|
|
|
|
/*
|
|
* if there was a previous node; link it and wait until reaching the
|
|
* head of the waitqueue.
|
|
*/
|
|
if (old & _Q_TAIL_MASK) {
|
|
int val;
|
|
|
|
prev = decode_tail(old, rqnodes);
|
|
|
|
/* Link @node into the waitqueue. */
|
|
WRITE_ONCE(prev->next, node);
|
|
|
|
val = arch_mcs_spin_lock_contended(&node->locked);
|
|
if (val == RES_TIMEOUT_VAL) {
|
|
ret = -EDEADLK;
|
|
goto waitq_timeout;
|
|
}
|
|
|
|
/*
|
|
* While waiting for the MCS lock, the next pointer may have
|
|
* been set by another lock waiter. We optimistically load
|
|
* the next pointer & prefetch the cacheline for writing
|
|
* to reduce latency in the upcoming MCS unlock operation.
|
|
*/
|
|
next = READ_ONCE(node->next);
|
|
if (next)
|
|
prefetchw(next);
|
|
}
|
|
|
|
/*
|
|
* we're at the head of the waitqueue, wait for the owner & pending to
|
|
* go away.
|
|
*
|
|
* *,x,y -> *,0,0
|
|
*
|
|
* this wait loop must use a load-acquire such that we match the
|
|
* store-release that clears the locked bit and create lock
|
|
* sequentiality; this is because the set_locked() function below
|
|
* does not imply a full barrier.
|
|
*
|
|
* We use RES_DEF_TIMEOUT * 2 as the duration, as RES_DEF_TIMEOUT is
|
|
* meant to span maximum allowed time per critical section, and we may
|
|
* have both the owner of the lock and the pending bit waiter ahead of
|
|
* us.
|
|
*/
|
|
RES_RESET_TIMEOUT(ts, RES_DEF_TIMEOUT * 2);
|
|
val = res_atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK) ||
|
|
RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_PENDING_MASK));
|
|
|
|
waitq_timeout:
|
|
if (ret) {
|
|
/*
|
|
* If the tail is still pointing to us, then we are the final waiter,
|
|
* and are responsible for resetting the tail back to 0. Otherwise, if
|
|
* the cmpxchg operation fails, we signal the next waiter to take exit
|
|
* and try the same. For a waiter with tail node 'n':
|
|
*
|
|
* n,*,* -> 0,*,*
|
|
*
|
|
* When performing cmpxchg for the whole word (NR_CPUS > 16k), it is
|
|
* possible locked/pending bits keep changing and we see failures even
|
|
* when we remain the head of wait queue. However, eventually,
|
|
* pending bit owner will unset the pending bit, and new waiters
|
|
* will queue behind us. This will leave the lock owner in
|
|
* charge, and it will eventually either set locked bit to 0, or
|
|
* leave it as 1, allowing us to make progress.
|
|
*
|
|
* We terminate the whole wait queue for two reasons. Firstly,
|
|
* we eschew per-waiter timeouts with one applied at the head of
|
|
* the wait queue. This allows everyone to break out faster
|
|
* once we've seen the owner / pending waiter not responding for
|
|
* the timeout duration from the head. Secondly, it avoids
|
|
* complicated synchronization, because when not leaving in FIFO
|
|
* order, prev's next pointer needs to be fixed up etc.
|
|
*/
|
|
if (!try_cmpxchg_tail(lock, tail, 0)) {
|
|
next = smp_cond_load_relaxed(&node->next, VAL);
|
|
WRITE_ONCE(next->locked, RES_TIMEOUT_VAL);
|
|
}
|
|
lockevent_inc(rqspinlock_lock_timeout);
|
|
goto err_release_node;
|
|
}
|
|
|
|
/*
|
|
* claim the lock:
|
|
*
|
|
* n,0,0 -> 0,0,1 : lock, uncontended
|
|
* *,*,0 -> *,*,1 : lock, contended
|
|
*
|
|
* If the queue head is the only one in the queue (lock value == tail)
|
|
* and nobody is pending, clear the tail code and grab the lock.
|
|
* Otherwise, we only need to grab the lock.
|
|
*/
|
|
|
|
/*
|
|
* Note: at this point: (val & _Q_PENDING_MASK) == 0, because of the
|
|
* above wait condition, therefore any concurrent setting of
|
|
* PENDING will make the uncontended transition fail.
|
|
*/
|
|
if ((val & _Q_TAIL_MASK) == tail) {
|
|
if (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))
|
|
goto release; /* No contention */
|
|
}
|
|
|
|
/*
|
|
* Either somebody is queued behind us or _Q_PENDING_VAL got set
|
|
* which will then detect the remaining tail and queue behind us
|
|
* ensuring we'll see a @next.
|
|
*/
|
|
set_locked(lock);
|
|
|
|
/*
|
|
* contended path; wait for next if not observed yet, release.
|
|
*/
|
|
if (!next)
|
|
next = smp_cond_load_relaxed(&node->next, (VAL));
|
|
|
|
arch_mcs_spin_unlock_contended(&next->locked);
|
|
|
|
release:
|
|
trace_contention_end(lock, 0);
|
|
|
|
/*
|
|
* release the node
|
|
*/
|
|
__this_cpu_dec(rqnodes[0].mcs.count);
|
|
return ret;
|
|
err_release_node:
|
|
trace_contention_end(lock, ret);
|
|
__this_cpu_dec(rqnodes[0].mcs.count);
|
|
err_release_entry:
|
|
release_held_lock_entry();
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(resilient_queued_spin_lock_slowpath);
|
|
|
|
#endif /* CONFIG_QUEUED_SPINLOCKS */
|
|
|
|
__bpf_kfunc_start_defs();
|
|
|
|
__bpf_kfunc int bpf_res_spin_lock(struct bpf_res_spin_lock *lock)
|
|
{
|
|
int ret;
|
|
|
|
BUILD_BUG_ON(sizeof(rqspinlock_t) != sizeof(struct bpf_res_spin_lock));
|
|
BUILD_BUG_ON(__alignof__(rqspinlock_t) != __alignof__(struct bpf_res_spin_lock));
|
|
|
|
preempt_disable();
|
|
ret = res_spin_lock((rqspinlock_t *)lock);
|
|
if (unlikely(ret)) {
|
|
preempt_enable();
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
__bpf_kfunc void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock)
|
|
{
|
|
res_spin_unlock((rqspinlock_t *)lock);
|
|
preempt_enable();
|
|
}
|
|
|
|
__bpf_kfunc int bpf_res_spin_lock_irqsave(struct bpf_res_spin_lock *lock, unsigned long *flags__irq_flag)
|
|
{
|
|
u64 *ptr = (u64 *)flags__irq_flag;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
preempt_disable();
|
|
local_irq_save(flags);
|
|
ret = res_spin_lock((rqspinlock_t *)lock);
|
|
if (unlikely(ret)) {
|
|
local_irq_restore(flags);
|
|
preempt_enable();
|
|
return ret;
|
|
}
|
|
*ptr = flags;
|
|
return 0;
|
|
}
|
|
|
|
__bpf_kfunc void bpf_res_spin_unlock_irqrestore(struct bpf_res_spin_lock *lock, unsigned long *flags__irq_flag)
|
|
{
|
|
u64 *ptr = (u64 *)flags__irq_flag;
|
|
unsigned long flags = *ptr;
|
|
|
|
res_spin_unlock((rqspinlock_t *)lock);
|
|
local_irq_restore(flags);
|
|
preempt_enable();
|
|
}
|
|
|
|
__bpf_kfunc_end_defs();
|
|
|
|
BTF_KFUNCS_START(rqspinlock_kfunc_ids)
|
|
BTF_ID_FLAGS(func, bpf_res_spin_lock, KF_RET_NULL)
|
|
BTF_ID_FLAGS(func, bpf_res_spin_unlock)
|
|
BTF_ID_FLAGS(func, bpf_res_spin_lock_irqsave, KF_RET_NULL)
|
|
BTF_ID_FLAGS(func, bpf_res_spin_unlock_irqrestore)
|
|
BTF_KFUNCS_END(rqspinlock_kfunc_ids)
|
|
|
|
static const struct btf_kfunc_id_set rqspinlock_kfunc_set = {
|
|
.owner = THIS_MODULE,
|
|
.set = &rqspinlock_kfunc_ids,
|
|
};
|
|
|
|
static __init int rqspinlock_register_kfuncs(void)
|
|
{
|
|
return register_btf_kfunc_id_set(BPF_PROG_TYPE_UNSPEC, &rqspinlock_kfunc_set);
|
|
}
|
|
late_initcall(rqspinlock_register_kfuncs);
|