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9525c66de3
Add documentation for AD7191 driver. Signed-off-by: Alisa-Dariana Roman <alisa.roman@analog.com> Reviewed-by: David Lechner<dlechner@baylibre.com> Link: https://patch.msgid.link/20250228141327.262488-4-alisa.roman@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
120 lines
3.3 KiB
ReStructuredText
120 lines
3.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-only
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=============
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AD7191 driver
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=============
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Device driver for Analog Devices AD7191 ADC.
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Supported devices
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=================
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* `AD7191 <https://www.analog.com/AD7191>`_
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The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA.
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It features two differential input channels, an internal temperature sensor, and
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configurable sampling rates.
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Devicetree
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==========
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Pin Configuration
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-----------------
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The driver supports both pin-strapped and GPIO-controlled configurations for ODR
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(Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These
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configurations are mutually exclusive - you must use either pin-strapped or GPIO
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control for each setting, not both.
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ODR Configuration
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^^^^^^^^^^^^^^^^^
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The ODR can be configured either through GPIO control or pin-strapping:
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- When using GPIO control, specify the "odr-gpios" property in the device tree
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- For pin-strapped configuration, specify the "adi,odr-value" property in the
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device tree
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Available ODR settings:
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- 120 Hz (ODR1=0, ODR2=0)
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- 60 Hz (ODR1=0, ODR2=1)
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- 50 Hz (ODR1=1, ODR2=0)
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- 10 Hz (ODR1=1, ODR2=1)
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PGA Configuration
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^^^^^^^^^^^^^^^^^
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The PGA can be configured either through GPIO control or pin-strapping:
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- When using GPIO control, specify the "pga-gpios" property in the device tree
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- For pin-strapped configuration, specify the "adi,pga-value" property in the
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device tree
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Available PGA gain settings:
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- 1x (PGA1=0, PGA2=0)
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- 8x (PGA1=0, PGA2=1)
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- 64x (PGA1=1, PGA2=0)
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- 128x (PGA1=1, PGA2=1)
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Clock Configuration
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-------------------
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The AD7191 supports both internal and external clock sources:
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- When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property
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needed)
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- When CLKSEL pin is tied HIGH: Requires external clock source
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- Can be a crystal between MCLK1 and MCLK2 pins
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- Or a CMOS-compatible clock driving MCLK2 pin
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- Must specify the "clocks" property in device tree when using external clock
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SPI Interface Requirements
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--------------------------
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The AD7191 has specific SPI interface requirements:
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- The DOUT/RDY output is dual-purpose and requires SPI bus locking
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- DOUT/RDY must be connected to an interrupt-capable GPIO
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- The SPI controller's chip select must be connected to the PDOWN pin of the ADC
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- When CS (PDOWN) is high, the device powers down and resets internal circuitry
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- SPI mode 3 operation (CPOL=1, CPHA=1) is required
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Power Supply Requirements
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-------------------------
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The device requires the following power supplies:
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- AVdd: Analog power supply
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- DVdd: Digital power supply
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- Vref: Reference voltage supply (external)
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All power supplies must be specified in the device tree.
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Channel Configuration
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=====================
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The device provides three channels:
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1. Temperature Sensor
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- 24-bit unsigned
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- Internal temperature measurement
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- Temperature in millidegrees Celsius
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2. Differential Input (AIN1-AIN2)
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- 24-bit unsigned
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- Differential voltage measurement
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- Configurable gain via PGA
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3. Differential Input (AIN3-AIN4)
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- 24-bit unsigned
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- Differential voltage measurement
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- Configurable gain via PGA
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Buffer Support
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==============
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This driver supports IIO triggered buffers. See Documentation/iio/iio_devbuf.rst
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for more information about IIO triggered buffers.
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