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This adds a new page to document how to use the ad4030 ADC driver Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-6-135dd66cab6a@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
181 lines
5.6 KiB
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181 lines
5.6 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-only
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=============
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AD4030 driver
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=============
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ADC driver for Analog Devices Inc. AD4030 and similar devices. The module name
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is ``ad4030``.
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Supported devices
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=================
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The following chips are supported by this driver:
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* `AD4030-24 <https://www.analog.com/AD4030-24>`_
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* `AD4032-24 <https://www.analog.com/AD4032-24>`_
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* `AD4630-16 <https://www.analog.com/AD4630-16>`_
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* `AD4630-24 <https://www.analog.com/AD4630-24>`_
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* `AD4632-16 <https://www.analog.com/AD4632-16>`_
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* `AD4632-24 <https://www.analog.com/AD4632-24>`_
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IIO channels
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============
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Each "hardware" channel as described in the datasheet is split in 2 IIO
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channels:
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- One channel for the differential data
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- One channel for the common byte.
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The possible IIO channels depending on the numbers of "hardware" channel are:
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+------------------------------------+------------------------------------+
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| 1 channel ADC | 2 channels ADC |
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+====================================+====================================+
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| - voltage0-voltage1 (differential) | - voltage0-voltage1 (differential) |
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| - voltage2 (common-mode) | - voltage2-voltage3 (differential) |
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| | - voltage4 (common-mode) |
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| | - voltage5 (common-mode) |
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+------------------------------------+------------------------------------+
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Labels
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------
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For ease of use, the IIO channels provide a label. For a differential channel,
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the label is ``differentialN`` where ``N`` is the "hardware" channel id. For a
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common-mode channel, the label is ``common-modeN`` where ``N`` is the
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"hardware" channel id.
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The possible labels are:
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+-----------------+-----------------+
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| 1 channel ADC | 2 channels ADC |
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+=================+=================+
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| - differential0 | - differential0 |
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| - common-mode0 | - differential1 |
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| | - common-mode0 |
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| | - common-mode1 |
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+-----------------+-----------------+
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Supported features
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==================
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SPI wiring modes
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----------------
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The driver currently supports the following SPI wiring configurations:
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One lane mode
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^^^^^^^^^^^^^
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In this mode, each channel has its own SDO line to send the conversion results.
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At the moment this mode can only be used on AD4030 which has one channel so only
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one SDO line is used.
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.. code-block::
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+-------------+ +-------------+
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| ADC | | HOST |
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| | | |
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| CNV |<--------| CNV |
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| CS |<--------| CS |
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| SDI |<--------| SDO |
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| SDO0 |-------->| SDI |
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| SCLK |<--------| SCLK |
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+-------------+ +-------------+
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Interleaved mode
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^^^^^^^^^^^^^^^^
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In this mode, both channels conversion results are bit interleaved one SDO line.
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As such the wiring is the same as `One lane mode`_.
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SPI Clock mode
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--------------
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Only the SPI clocking mode is supported.
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Output modes
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------------
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There are more exposed IIO channels than channels as describe in the devices
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datasheet. This is due to the `Differential data + common-mode`_ encoding
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2 types of information in one conversion result. As such a "device" channel
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provides 2 IIO channels, one for the differential data and one for the common
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byte.
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Differential data
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^^^^^^^^^^^^^^^^^
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This mode is selected when:
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- Only differential channels are enabled in a buffered read
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- Oversampling attribute is set to 1
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Differential data + common-mode
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This mode is selected when:
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- Differential and common-mode channels are enabled in a buffered read
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- Oversampling attribute is set to 1
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For the 24-bits chips, this mode is also available with 16-bits differential
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data but is not selectable yet.
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Averaged differential data
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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This mode is selected when:
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- Only differential channels are selected enabled in a buffered read
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- Oversampling attribute is greater than 1
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Digital Gain and Offset
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-----------------------
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Each differential data channel has a 16-bits unsigned configurable hardware
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gain applied to it. By default it's equal to 1. Note that applying gain can
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cause numerical saturation.
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Each differential data channel has a signed configurable hardware offset.
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For the ADCs ending in ``-24``, the gain is encoded on 24-bits.
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Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note that
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applying an offset can cause numerical saturation.
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The final differential data returned by the ADC is computed by first applying
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the gain, then the offset.
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The gain is controlled by the ``calibscale`` IIO attribute while the offset is
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controlled by the ``calibbias`` attribute.
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Reference voltage
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-----------------
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The chip supports an external reference voltage via the ``REF`` input or an
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internal buffered reference voltage via the ``REFIN`` input. The driver looks
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at the device tree to determine which is being used. If ``ref-supply`` is
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present, then the external reference voltage is used and the internal buffer is
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disabled. If ``refin-supply`` is present, then the internal buffered reference
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voltage is used.
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Reset
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-----
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Both hardware and software reset are supported. The driver looks first at the
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device tree to see if the ``reset-gpio`` is populated.
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If not present, the driver will fallback to a software reset by wiring to the
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device's registers.
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Unimplemented features
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----------------------
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- ``BUSY`` indication
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- Additional wiring modes
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- Additional clock modes
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- Differential data 16-bits + common-mode for 24-bits chips
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- Overrange events
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- Test patterns
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