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spi: sophgo: add SG2044 SPI NOR controller driver
Add support for SG2044 SPI NOR controller in Sophgo SoC. Signed-off-by: Longbin Li <looong.bin@gmail.com> Link: https://patch.msgid.link/20250304083548.10101-3-looong.bin@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Longbin Li
Mark Brown
parent
9f95e2dff3
commit
de16c322ee
@ -1034,6 +1034,15 @@ config SPI_SN_F_OSPI
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for connecting an SPI Flash memory over up to 8-bit wide bus.
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It supports indirect access mode only.
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config SPI_SG2044_NOR
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tristate "SG2044 SPI NOR Controller"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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This enables support for the SG2044 SPI NOR controller,
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which supports Dual/Quad read and write operations while
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also supporting 3Byte address devices and 4Byte address
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devices.
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config SPI_SPRD
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tristate "Spreadtrum SPI controller"
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depends on ARCH_SPRD || COMPILE_TEST
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@ -136,6 +136,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
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obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
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obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
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obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o
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obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
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obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
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obj-$(CONFIG_SPI_STM32) += spi-stm32.o
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500
drivers/spi/spi-sg2044-nor.c
Normal file
500
drivers/spi/spi-sg2044-nor.c
Normal file
@ -0,0 +1,500 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SG2044 SPI NOR controller driver
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*
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* Copyright (c) 2025 Longbin Li <looong.bin@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi-mem.h>
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/* Hardware register definitions */
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#define SPIFMC_CTRL 0x00
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#define SPIFMC_CTRL_CPHA BIT(12)
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#define SPIFMC_CTRL_CPOL BIT(13)
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#define SPIFMC_CTRL_HOLD_OL BIT(14)
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#define SPIFMC_CTRL_WP_OL BIT(15)
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#define SPIFMC_CTRL_LSBF BIT(20)
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#define SPIFMC_CTRL_SRST BIT(21)
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#define SPIFMC_CTRL_SCK_DIV_SHIFT 0
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#define SPIFMC_CTRL_FRAME_LEN_SHIFT 16
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#define SPIFMC_CTRL_SCK_DIV_MASK 0x7FF
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#define SPIFMC_CE_CTRL 0x04
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#define SPIFMC_CE_CTRL_CEMANUAL BIT(0)
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#define SPIFMC_CE_CTRL_CEMANUAL_EN BIT(1)
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#define SPIFMC_DLY_CTRL 0x08
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#define SPIFMC_CTRL_FM_INTVL_MASK 0x000f
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#define SPIFMC_CTRL_FM_INTVL BIT(0)
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#define SPIFMC_CTRL_CET_MASK 0x0f00
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#define SPIFMC_CTRL_CET BIT(8)
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#define SPIFMC_DMMR 0x0c
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#define SPIFMC_TRAN_CSR 0x10
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#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK GENMASK(1, 0)
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#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0)
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#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1)
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#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3)
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#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4)
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#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4)
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#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4)
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#define SPIFMC_TRAN_CSR_DMA_EN BIT(6)
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#define SPIFMC_TRAN_CSR_MISO_LEVEL BIT(7)
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#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK GENMASK(10, 8)
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#define SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT 8
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#define SPIFMC_TRAN_CSR_WITH_CMD BIT(11)
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#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK GENMASK(13, 12)
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#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE (0x00 << 12)
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#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_2_BYTE (0x01 << 12)
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#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE (0x02 << 12)
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#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE (0x03 << 12)
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#define SPIFMC_TRAN_CSR_GO_BUSY BIT(15)
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#define SPIFMC_TRAN_CSR_ADDR4B_SHIFT 20
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#define SPIFMC_TRAN_CSR_CMD4B_SHIFT 21
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#define SPIFMC_TRAN_NUM 0x14
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#define SPIFMC_FIFO_PORT 0x18
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#define SPIFMC_FIFO_PT 0x20
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#define SPIFMC_INT_STS 0x28
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#define SPIFMC_INT_TRAN_DONE BIT(0)
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#define SPIFMC_INT_RD_FIFO BIT(2)
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#define SPIFMC_INT_WR_FIFO BIT(3)
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#define SPIFMC_INT_RX_FRAME BIT(4)
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#define SPIFMC_INT_TX_FRAME BIT(5)
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#define SPIFMC_INT_EN 0x2c
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#define SPIFMC_INT_TRAN_DONE_EN BIT(0)
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#define SPIFMC_INT_RD_FIFO_EN BIT(2)
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#define SPIFMC_INT_WR_FIFO_EN BIT(3)
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#define SPIFMC_INT_RX_FRAME_EN BIT(4)
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#define SPIFMC_INT_TX_FRAME_EN BIT(5)
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#define SPIFMC_OPT 0x030
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#define SPIFMC_OPT_DISABLE_FIFO_FLUSH BIT(1)
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#define SPIFMC_MAX_FIFO_DEPTH 8
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#define SPIFMC_MAX_READ_SIZE 0x10000
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struct sg2044_spifmc {
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struct spi_controller *ctrl;
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void __iomem *io_base;
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struct device *dev;
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struct mutex lock;
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struct clk *clk;
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};
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static int sg2044_spifmc_wait_int(struct sg2044_spifmc *spifmc, u8 int_type)
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{
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u32 stat;
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return readl_poll_timeout(spifmc->io_base + SPIFMC_INT_STS, stat,
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(stat & int_type), 0, 1000000);
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}
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static int sg2044_spifmc_wait_xfer_size(struct sg2044_spifmc *spifmc,
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int xfer_size)
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{
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u8 stat;
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return readl_poll_timeout(spifmc->io_base + SPIFMC_FIFO_PT, stat,
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((stat & 0xf) == xfer_size), 1, 1000000);
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}
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static u32 sg2044_spifmc_init_reg(struct sg2044_spifmc *spifmc)
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{
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u32 reg;
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reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
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reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK |
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SPIFMC_TRAN_CSR_FAST_MODE |
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SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT |
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SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT |
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SPIFMC_TRAN_CSR_DMA_EN |
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SPIFMC_TRAN_CSR_ADDR_BYTES_MASK |
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SPIFMC_TRAN_CSR_WITH_CMD |
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SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK);
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writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
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return reg;
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}
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static ssize_t sg2044_spifmc_read_64k(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op, loff_t from,
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size_t len, u_char *buf)
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{
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int xfer_size, offset;
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u32 reg;
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int ret;
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int i;
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reg = sg2044_spifmc_init_reg(spifmc);
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reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
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reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE;
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reg |= SPIFMC_TRAN_CSR_WITH_CMD;
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = op->addr.nbytes - 1; i >= 0; i--)
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writeb((from >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = 0; i < op->dummy.nbytes; i++)
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writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
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writel(0, spifmc->io_base + SPIFMC_INT_STS);
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reg |= SPIFMC_TRAN_CSR_GO_BUSY;
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writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
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ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_RD_FIFO);
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if (ret < 0)
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return ret;
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offset = 0;
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while (offset < len) {
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xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset);
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ret = sg2044_spifmc_wait_xfer_size(spifmc, xfer_size);
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if (ret < 0)
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return ret;
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for (i = 0; i < xfer_size; i++)
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buf[i + offset] = readb(spifmc->io_base + SPIFMC_FIFO_PORT);
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offset += xfer_size;
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}
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ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
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if (ret < 0)
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return ret;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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return len;
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}
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static ssize_t sg2044_spifmc_read(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op)
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{
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size_t xfer_size;
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size_t offset;
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loff_t from = op->addr.val;
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size_t len = op->data.nbytes;
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int ret;
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u8 *din = op->data.buf.in;
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offset = 0;
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while (offset < len) {
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xfer_size = min_t(size_t, SPIFMC_MAX_READ_SIZE, len - offset);
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ret = sg2044_spifmc_read_64k(spifmc, op, from, xfer_size, din);
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if (ret < 0)
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return ret;
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offset += xfer_size;
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din += xfer_size;
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from += xfer_size;
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}
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return 0;
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}
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static ssize_t sg2044_spifmc_write(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op)
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{
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size_t xfer_size;
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const u8 *dout = op->data.buf.out;
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int i, offset;
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size_t ret;
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u32 reg;
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reg = sg2044_spifmc_init_reg(spifmc);
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reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
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reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE;
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reg |= SPIFMC_TRAN_CSR_WITH_CMD;
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = op->addr.nbytes - 1; i >= 0; i--)
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writeb((op->addr.val >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = 0; i < op->dummy.nbytes; i++)
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writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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writel(0, spifmc->io_base + SPIFMC_INT_STS);
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writel(op->data.nbytes, spifmc->io_base + SPIFMC_TRAN_NUM);
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reg |= SPIFMC_TRAN_CSR_GO_BUSY;
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writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
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ret = sg2044_spifmc_wait_xfer_size(spifmc, 0);
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if (ret < 0)
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return ret;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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offset = 0;
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while (offset < op->data.nbytes) {
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xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, op->data.nbytes - offset);
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ret = sg2044_spifmc_wait_xfer_size(spifmc, 0);
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if (ret < 0)
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return ret;
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for (i = 0; i < xfer_size; i++)
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writeb(dout[i + offset], spifmc->io_base + SPIFMC_FIFO_PORT);
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offset += xfer_size;
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}
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ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
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if (ret < 0)
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return ret;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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return 0;
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}
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static ssize_t sg2044_spifmc_tran_cmd(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op)
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{
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int i, ret;
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u32 reg;
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reg = sg2044_spifmc_init_reg(spifmc);
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reg |= (op->addr.nbytes + op->dummy.nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT;
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reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE;
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reg |= SPIFMC_TRAN_CSR_WITH_CMD;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = op->addr.nbytes - 1; i >= 0; i--)
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writeb((op->addr.val >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = 0; i < op->dummy.nbytes; i++)
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writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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writel(0, spifmc->io_base + SPIFMC_INT_STS);
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reg |= SPIFMC_TRAN_CSR_GO_BUSY;
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writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
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ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
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if (ret < 0)
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return ret;
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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return 0;
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}
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static void sg2044_spifmc_trans(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op)
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{
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if (op->data.dir == SPI_MEM_DATA_IN)
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sg2044_spifmc_read(spifmc, op);
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else if (op->data.dir == SPI_MEM_DATA_OUT)
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sg2044_spifmc_write(spifmc, op);
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else
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sg2044_spifmc_tran_cmd(spifmc, op);
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}
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static ssize_t sg2044_spifmc_trans_reg(struct sg2044_spifmc *spifmc,
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const struct spi_mem_op *op)
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{
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const u8 *dout = NULL;
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u8 *din = NULL;
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size_t len = op->data.nbytes;
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int ret, i;
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u32 reg;
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if (op->data.dir == SPI_MEM_DATA_IN)
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din = op->data.buf.in;
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else
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dout = op->data.buf.out;
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reg = sg2044_spifmc_init_reg(spifmc);
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reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE;
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reg |= SPIFMC_TRAN_CSR_WITH_CMD;
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if (din) {
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reg |= SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT;
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
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writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT);
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} else {
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/*
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* If write values to the Status Register,
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* configure TRAN_CSR register as the same as
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* sg2044_spifmc_read_reg.
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*/
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if (op->cmd.opcode == 0x01) {
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX;
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reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX;
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writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
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}
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}
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writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
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writeb(op->cmd.opcode, spifmc->io_base + SPIFMC_FIFO_PORT);
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for (i = 0; i < len; i++) {
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if (din)
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writeb(0xff, spifmc->io_base + SPIFMC_FIFO_PORT);
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else
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writeb(dout[i], spifmc->io_base + SPIFMC_FIFO_PORT);
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}
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writel(0, spifmc->io_base + SPIFMC_INT_STS);
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writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
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reg |= SPIFMC_TRAN_CSR_GO_BUSY;
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writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
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ret = sg2044_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE);
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if (ret < 0)
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return ret;
|
||||
|
||||
if (din) {
|
||||
while (len--)
|
||||
*din++ = readb(spifmc->io_base + SPIFMC_FIFO_PORT);
|
||||
}
|
||||
|
||||
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sg2044_spifmc_exec_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct sg2044_spifmc *spifmc;
|
||||
|
||||
spifmc = spi_controller_get_devdata(mem->spi->controller);
|
||||
|
||||
mutex_lock(&spifmc->lock);
|
||||
|
||||
if (op->addr.nbytes == 0)
|
||||
sg2044_spifmc_trans_reg(spifmc, op);
|
||||
else
|
||||
sg2044_spifmc_trans(spifmc, op);
|
||||
|
||||
mutex_unlock(&spifmc->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops sg2044_spifmc_mem_ops = {
|
||||
.exec_op = sg2044_spifmc_exec_op,
|
||||
};
|
||||
|
||||
static void sg2044_spifmc_init(struct sg2044_spifmc *spifmc)
|
||||
{
|
||||
u32 tran_csr;
|
||||
u32 reg;
|
||||
|
||||
writel(0, spifmc->io_base + SPIFMC_DMMR);
|
||||
|
||||
reg = readl(spifmc->io_base + SPIFMC_CTRL);
|
||||
reg |= SPIFMC_CTRL_SRST;
|
||||
reg &= ~(SPIFMC_CTRL_SCK_DIV_MASK);
|
||||
reg |= 1;
|
||||
writel(reg, spifmc->io_base + SPIFMC_CTRL);
|
||||
|
||||
writel(0, spifmc->io_base + SPIFMC_CE_CTRL);
|
||||
|
||||
tran_csr = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
|
||||
tran_csr |= (0 << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT);
|
||||
tran_csr |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE;
|
||||
tran_csr |= SPIFMC_TRAN_CSR_WITH_CMD;
|
||||
writel(tran_csr, spifmc->io_base + SPIFMC_TRAN_CSR);
|
||||
}
|
||||
|
||||
static int sg2044_spifmc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *ctrl;
|
||||
struct sg2044_spifmc *spifmc;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*spifmc));
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
spifmc = spi_controller_get_devdata(ctrl);
|
||||
dev_set_drvdata(&pdev->dev, ctrl);
|
||||
|
||||
spifmc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
|
||||
if (IS_ERR(spifmc->clk))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(spifmc->clk),
|
||||
"%s: Cannot get and enable AHB clock\n",
|
||||
__func__);
|
||||
|
||||
spifmc->dev = &pdev->dev;
|
||||
spifmc->ctrl = ctrl;
|
||||
|
||||
spifmc->io_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
ctrl->num_chipselect = 1;
|
||||
ctrl->dev.of_node = pdev->dev.of_node;
|
||||
ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
ctrl->auto_runtime_pm = false;
|
||||
ctrl->mem_ops = &sg2044_spifmc_mem_ops;
|
||||
ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD;
|
||||
|
||||
mutex_init(&spifmc->lock);
|
||||
|
||||
sg2044_spifmc_init(spifmc);
|
||||
sg2044_spifmc_init_reg(spifmc);
|
||||
|
||||
ret = devm_spi_register_controller(&pdev->dev, ctrl);
|
||||
if (ret) {
|
||||
mutex_destroy(&spifmc->lock);
|
||||
dev_err(&pdev->dev, "spi_register_controller failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sg2044_spifmc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sg2044_spifmc *spifmc = platform_get_drvdata(pdev);
|
||||
|
||||
mutex_destroy(&spifmc->lock);
|
||||
}
|
||||
|
||||
static const struct of_device_id sg2044_spifmc_match[] = {
|
||||
{ .compatible = "sophgo,sg2044-spifmc-nor" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sg2044_spifmc_match);
|
||||
|
||||
static struct platform_driver sg2044_nor_driver = {
|
||||
.driver = {
|
||||
.name = "sg2044,spifmc-nor",
|
||||
.of_match_table = sg2044_spifmc_match,
|
||||
},
|
||||
.probe = sg2044_spifmc_probe,
|
||||
.remove = sg2044_spifmc_remove,
|
||||
};
|
||||
module_platform_driver(sg2044_nor_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SG2044 SPI NOR controller driver");
|
||||
MODULE_AUTHOR("Longbin Li <looong.bin@gmail.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
x
Reference in New Issue
Block a user