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Devicetree fixes for v6.15, part 1:

Browse Source 
- A couple of maintainers updates
 
 - Remove obsolete Renesas TPU timer binding
 
 - Add i.MX94 support to nxp,sysctr-timer and fsl,irqsteer
 
 - Add support for 'data-lanes' property in fsl,imx8mq-nwl-dsi binding
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Merge tag 'devicetree-fixes-for-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree fixes from Rob Herring:

 - A couple of maintainers updates

 - Remove obsolete Renesas TPU timer binding

 - Add i.MX94 support to nxp,sysctr-timer and fsl,irqsteer

 - Add support for 'data-lanes' property in fsl,imx8mq-nwl-dsi binding

* tag 'devicetree-fixes-for-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry
  dt-bindings: timer: renesas,tpu: remove obsolete binding
  dt-bindings: timer: nxp,sysctr-timer: Add i.MX94 support
  dt-bindings: interrupt-controller: fsl,irqsteer: Add i.MX94 support
  dt-bindings: display: nwl-dsi: Allow 'data-lanes' property for port@1
  dt-bindings: xilinx: Remove myself from maintainership
This commit is contained in:
Linus Torvalds 2025-04-16 13:34:18 -07:00
commit c1336865c4
12 changed files with 27 additions and 76 deletions
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1
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |

18
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
View File

@ -111,11 +111,27 @@ properties:
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
DSI output port node to the panel or the next bridge
in the chain
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- port@0
- port@1

1
Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
View File

@ -12,7 +12,6 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:

1
Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
View File

@ -19,6 +19,7 @@ properties:
- fsl,imx8mp-irqsteer
- fsl,imx8qm-irqsteer
- fsl,imx8qxp-irqsteer
- fsl,imx94-irqsteer
- const: fsl,imx-irqsteer
reg:

9
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
View File

@ -9,15 +9,6 @@ title: Renesas R-Car Timer Pulse Unit PWM Controller
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
select:
properties:
compatible:
contains:
const: renesas,tpu
required:
- compatible
- '#pwm-cells'
properties:
compatible:
items:

1
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq UltraScale+ MPSoC and Versal reset
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |

2
Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape Reset Registers Module
maintainers:
- Frank Li
- Frank Li <Frank.Li@nxp.com>
description:
Reset Module includes chip reset, service processor control and Reset Control

11
Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
View File

@ -18,9 +18,14 @@ description: |
properties:
compatible:
enum:
- nxp,imx95-sysctr-timer
- nxp,sysctr-timer
oneOf:
- enum:
- nxp,imx95-sysctr-timer
- nxp,sysctr-timer
- items:
- enum:
- nxp,imx94-sysctr-timer
- const: nxp,imx95-sysctr-timer
reg:
maxItems: 1

56
Documentation/devicetree/bindings/timer/renesas,tpu.yaml
View File

@ -1,56 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas H8/300 Timer Pulse Unit
maintainers:
- Yoshinori Sato <ysato@users.sourceforge.jp>
description:
The TPU is a 16bit timer/counter with configurable clock inputs and
programmable compare match.
This implementation supports only cascade mode.
select:
properties:
compatible:
contains:
const: renesas,tpu
'#pwm-cells': false
required:
- compatible
properties:
compatible:
const: renesas,tpu
reg:
items:
- description: First channel
- description: Second channel
clocks:
maxItems: 1
clock-names:
const: fck
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
tpu: tpu@ffffe0 {
compatible = "renesas,tpu";
reg = <0xffffe0 16>, <0xfffff0 12>;
clocks = <&pclk>;
clock-names = "fck";
};

1
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SuperSpeed DWC3 USB SoC controller
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:

1
Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
View File

@ -17,7 +17,6 @@ description:
maintainers:
- Michal Simek <michal.simek@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:

1
Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
View File

@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx udc controller
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties: