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Bug fixes for NTB Switchtec driver mw negative shift, Intel NTB link
status db, ntb_perf double unmap (in error case), and MSI 64bit arithmetic. Also, add new AMD NTB PCI IDs, update AMD NTB maintainer, and pull in patch to reduce the stack usage in IDT driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEoE9b9c3U2JxX98mqbmZLrHqL0iMFAmfazJIACgkQbmZLrHqL 0iPRUA//T5bOCQeW/NEKZM38/t4NFAfzcmbRc0RmDwndwO0P7kWTST2ObFbm1LLt TiMiCB+RPGupyMhALMqB0hHtDf/WqFz31ZcEt7TVDU38YjDi/0DIo4+3P0JsMItA mqG3XExpHdfQXkGj52wwADrrxZnijaR0vuQuB02HYswg3lIWUH/TJe1jM9c0cKTF DIZMwgF7EFiacl7CC2fxk/GtjqdKkQKZI6d78pQdyzY28wkb5tixntOofLfj6b8k buZwYZxya6CnY317BVGKK0qIoMJWuBSGAcNlWu4DZru2XL97Ht5yHa6PdQX6zR29 wiS7n5kTZgjPwLjQvzt4t9urEr752lAEXLE3SN8a9ZFQRohTfiK1FIjU3FJPirV0 ykoYtHWFoJFSIEkSbTvTzV2Wlq9ilcaJ2K2PA2K1hutaVb766PPUy9hZf7uFeeD/ PQ3nSGVHYJwFi08MR3NjtHvtiDxfXGQ1od/F+1HSPFgqNte0cB07Si25K5H55Jv1 /NjKbqvxjVEGSY9BMXDkZ3zYlFru+LKTBPkmlqJRu3Pb0+6DwJpyowS2Z4Qt+WAn HiT1kbzU/9i+SXFNJfC91PIeEfxdigj91ZXNbdoWjVNkpjx5v3jLbDuFnqT4xL23 1Q1XGul83RtmYQqCvkAzfTw2K1gx29t+w56tIAeWyNAHgn/I24s= =N7zn -----END PGP SIGNATURE----- Merge tag 'ntb-6.15' of https://github.com/jonmason/ntb Pull ntb fixes from Jon Mason: "Bug fixes for NTB Switchtec driver mw negative shift, Intel NTB link status db, ntb_perf double unmap (in error case), and MSI 64bit arithmetic. Also, add new AMD NTB PCI IDs, update AMD NTB maintainer, and pull in patch to reduce the stack usage in IDT driver" * tag 'ntb-6.15' of https://github.com/jonmason/ntb: ntb_hw_amd: Add NTB PCI ID for new gen CPU ntb: reduce stack usage in idt_scan_mws ntb: use 64-bit arithmetic for the MSI doorbell mask MAINTAINERS: Update AMD NTB maintainers ntb_perf: Delete duplicate dmaengine_unmap_put() call in perf_copy_chunk() ntb: intel: Fix using link status DB's ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans
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commit
a52a3c18cd
@ -17244,7 +17244,6 @@ F: Documentation/core-api/symbol-namespaces.rst
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F: scripts/nsdeps
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NTB AMD DRIVER
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M: Sanjay R Mehta <sanju.mehta@amd.com>
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M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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L: ntb@lists.linux.dev
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S: Supported
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@ -1318,6 +1318,7 @@ static const struct pci_device_id amd_ntb_pci_tbl[] = {
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{ PCI_VDEVICE(AMD, 0x148b), (kernel_ulong_t)&dev_data[1] },
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{ PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] },
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{ PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] },
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{ PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] },
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{ PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] },
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{ 0, }
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};
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@ -1041,7 +1041,7 @@ static inline char *idt_get_mw_name(enum idt_mw_type mw_type)
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static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,
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unsigned char *mw_cnt)
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{
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struct idt_mw_cfg mws[IDT_MAX_NR_MWS], *ret_mws;
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struct idt_mw_cfg *mws;
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const struct idt_ntb_bar *bars;
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enum idt_mw_type mw_type;
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unsigned char widx, bidx, en_cnt;
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@ -1049,6 +1049,11 @@ static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,
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int aprt_size;
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u32 data;
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mws = devm_kcalloc(&ndev->ntb.pdev->dev, IDT_MAX_NR_MWS,
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sizeof(*mws), GFP_KERNEL);
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if (!mws)
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return ERR_PTR(-ENOMEM);
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/* Retrieve the array of the BARs registers */
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bars = portdata_tbl[port].bars;
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@ -1103,16 +1108,7 @@ static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port,
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}
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}
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/* Allocate memory for memory window descriptors */
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ret_mws = devm_kcalloc(&ndev->ntb.pdev->dev, *mw_cnt, sizeof(*ret_mws),
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GFP_KERNEL);
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if (!ret_mws)
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return ERR_PTR(-ENOMEM);
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/* Copy the info of detected memory windows */
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memcpy(ret_mws, mws, (*mw_cnt)*sizeof(*ret_mws));
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return ret_mws;
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return mws;
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}
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/*
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@ -215,6 +215,9 @@ static int gen3_init_ntb(struct intel_ntb_dev *ndev)
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}
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ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
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/* Make sure we are not using DB's used for link status */
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if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
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ndev->db_valid_mask &= ~ndev->db_link_mask;
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ndev->reg->db_iowrite(ndev->db_valid_mask,
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ndev->self_mmio +
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@ -288,7 +288,7 @@ static int switchtec_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx,
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if (size != 0 && xlate_pos < 12)
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return -EINVAL;
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if (!IS_ALIGNED(addr, BIT_ULL(xlate_pos))) {
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if (xlate_pos >= 0 && !IS_ALIGNED(addr, BIT_ULL(xlate_pos))) {
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/*
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* In certain circumstances we can get a buffer that is
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* not aligned to its size. (Most of the time
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@ -1353,7 +1353,7 @@ static int ntb_transport_probe(struct ntb_client *self, struct ntb_dev *ndev)
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qp_count = ilog2(qp_bitmap);
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if (nt->use_msi) {
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qp_count -= 1;
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nt->msi_db_mask = 1 << qp_count;
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nt->msi_db_mask = BIT_ULL(qp_count);
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ntb_db_clear_mask(ndev, nt->msi_db_mask);
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}
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@ -839,10 +839,8 @@ static int perf_copy_chunk(struct perf_thread *pthr,
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dma_set_unmap(tx, unmap);
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ret = dma_submit_error(dmaengine_submit(tx));
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if (ret) {
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dmaengine_unmap_put(unmap);
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if (ret)
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goto err_free_resource;
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}
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dmaengine_unmap_put(unmap);
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