mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/
synced 2025-04-19 20:58:31 +09:00
s390 updates for 6.15-rc2
- Add IBM z17 bits:
- Setup elf_platform for new machine types
- Allow to compile the kernel with z17 optimizations
- Add new performance counters
- Fix mismatch between indicator bits and queue indexes in virtio CCW code
- Fix double free in pmu setup error path
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEECMNfWEw3SLnmiLkZIg7DeRspbsIFAmf43kgACgkQIg7DeRsp
bsLohA//Xrq2gP2vCHEpfrMIpcIOf0sb71uBCr9w6KIxCHtvF5fhJl/v/9pWrm1f
XAXYBFuuzHkAou9fnTyyhW74KtgZ7hgl6rwJNAvk/ah/P5WAoQQGFxSxvm6y70xK
frsr1Rr7EbeoyLTPVn4H50bvJNBPXMk6MCjf69gpuGSYJ4l7Y1hgc8l7qenDdlRw
Qi8raGBCEy3RcVIxmxLqbxjsSCNjbd97lcCL4kJPRFjQJCuEvqsoEaSXta8ymXpl
y9n4sLfMIKGTY1M1DUiIDSjvTQwukh+hSsV6BPYE2w++4BZV1RFXBV2kRkXPowvg
9ptOWHk6qumOJlWJjHTYoMBwdzlBI04swB1IlLDCsguZuM0ibmeR09OGSTACXc8u
vm4eAxt0DgOZVE1KIs1QlcMUeJ8pYA5PR1MdCVpyy/fv1V/1iUQoyn0CJC2jVA26
hm/CmFavumWipw3gXIGmq7wkDZIoKHeOnmL2BGWdoScftz9PRkhCgybeeRQXtQVp
Nx8VTopXG+1b00CHMqDGjiVXhsYaYDr4MNyWo45F09tDo8O0MoKK+EssUs+i1/fD
eR5vBOhSlPunsv0bPKCJGb0WlSPbGA7a1g1n8bxQSBeM05WaYOTgijLfjEDxXML+
TRsxMsJP0SoSVRpGDBMZF1LATAROMWYACutAO+6PXBbuZULgK9I=
=HxI1
-----END PGP SIGNATURE-----
Merge tag 's390-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
Pull s390 updates from Heiko Carstens:
"Note that besides two bug fixes this includes three commits for IBM
z17, which was announced this week.
- Add IBM z17 bits:
- Setup elf_platform for new machine types
- Allow to compile the kernel with z17 optimizations
- Add new performance counters
- Fix mismatch between indicator bits and queue indexes in virtio CCW code
- Fix double free in pmu setup error path"
* tag 's390-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
s390/cpumf: Fix double free on error in cpumf_pmu_event_init()
s390/cpumf: Update CPU Measurement facility extended counter set support
s390: Allow to compile with z17 optimizations
s390: Add z17 elf platform
s390/virtio_ccw: Don't allocate/assign airqs for non-existing queues
This commit is contained in:
Linus Torvalds
commit
9b03fa105c
@ -332,6 +332,10 @@ config HAVE_MARCH_Z16_FEATURES
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def_bool n
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select HAVE_MARCH_Z15_FEATURES
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config HAVE_MARCH_Z17_FEATURES
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def_bool n
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select HAVE_MARCH_Z16_FEATURES
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choice
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prompt "Processor type"
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default MARCH_Z196
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@ -397,6 +401,14 @@ config MARCH_Z16
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Select this to enable optimizations for IBM z16 (3931 and
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3932 series).
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config MARCH_Z17
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bool "IBM z17"
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select HAVE_MARCH_Z17_FEATURES
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depends on $(cc-option,-march=z17)
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help
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Select this to enable optimizations for IBM z17 (9175 and
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9176 series).
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endchoice
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config MARCH_Z10_TUNE
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@ -420,6 +432,9 @@ config MARCH_Z15_TUNE
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config MARCH_Z16_TUNE
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def_bool TUNE_Z16 || MARCH_Z16 && TUNE_DEFAULT
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config MARCH_Z17_TUNE
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def_bool TUNE_Z17 || MARCH_Z17 && TUNE_DEFAULT
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choice
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prompt "Tune code generation"
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default TUNE_DEFAULT
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@ -464,6 +479,10 @@ config TUNE_Z16
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bool "IBM z16"
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depends on $(cc-option,-mtune=z16)
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config TUNE_Z17
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bool "IBM z17"
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depends on $(cc-option,-mtune=z17)
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endchoice
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config 64BIT
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@ -48,6 +48,7 @@ mflags-$(CONFIG_MARCH_Z13) := -march=z13
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mflags-$(CONFIG_MARCH_Z14) := -march=z14
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mflags-$(CONFIG_MARCH_Z15) := -march=z15
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mflags-$(CONFIG_MARCH_Z16) := -march=z16
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mflags-$(CONFIG_MARCH_Z17) := -march=z17
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export CC_FLAGS_MARCH := $(mflags-y)
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@ -61,6 +62,7 @@ cflags-$(CONFIG_MARCH_Z13_TUNE) += -mtune=z13
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cflags-$(CONFIG_MARCH_Z14_TUNE) += -mtune=z14
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cflags-$(CONFIG_MARCH_Z15_TUNE) += -mtune=z15
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cflags-$(CONFIG_MARCH_Z16_TUNE) += -mtune=z16
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cflags-$(CONFIG_MARCH_Z17_TUNE) += -mtune=z17
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cflags-y += -Wa,-I$(srctree)/arch/$(ARCH)/include
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@ -33,6 +33,10 @@
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#define MARCH_HAS_Z16_FEATURES 1
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#endif
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#ifdef CONFIG_HAVE_MARCH_Z17_FEATURES
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#define MARCH_HAS_Z17_FEATURES 1
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#endif
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#endif /* __DECOMPRESSOR */
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#endif /* __ASM_S390_MARCH_H */
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@ -442,7 +442,7 @@ static void cpum_cf_make_setsize(enum cpumf_ctr_set ctrset)
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ctrset_size = 48;
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else if (cpumf_ctr_info.csvn >= 3 && cpumf_ctr_info.csvn <= 5)
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ctrset_size = 128;
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else if (cpumf_ctr_info.csvn == 6 || cpumf_ctr_info.csvn == 7)
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else if (cpumf_ctr_info.csvn >= 6 && cpumf_ctr_info.csvn <= 8)
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ctrset_size = 160;
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break;
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case CPUMF_CTR_SET_MT_DIAG:
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@ -858,18 +858,13 @@ static int cpumf_pmu_event_type(struct perf_event *event)
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static int cpumf_pmu_event_init(struct perf_event *event)
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{
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unsigned int type = event->attr.type;
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int err;
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int err = -ENOENT;
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if (type == PERF_TYPE_HARDWARE || type == PERF_TYPE_RAW)
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err = __hw_perf_event_init(event, type);
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else if (event->pmu->type == type)
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/* Registered as unknown PMU */
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err = __hw_perf_event_init(event, cpumf_pmu_event_type(event));
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else
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return -ENOENT;
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if (unlikely(err) && event->destroy)
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event->destroy(event);
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return err;
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}
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@ -1819,8 +1814,6 @@ static int cfdiag_event_init(struct perf_event *event)
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event->destroy = hw_perf_event_destroy;
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err = cfdiag_event_init2(event);
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if (unlikely(err))
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event->destroy(event);
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out:
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return err;
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}
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@ -237,7 +237,6 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
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CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
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CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
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CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
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CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
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@ -365,6 +364,83 @@ CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
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CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
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CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
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CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
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CPUMF_EVENT_ATTR(cf_z17, L1D_RO_EXCL_WRITES, 0x0080);
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CPUMF_EVENT_ATTR(cf_z17, DTLB2_WRITES, 0x0081);
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CPUMF_EVENT_ATTR(cf_z17, DTLB2_MISSES, 0x0082);
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CPUMF_EVENT_ATTR(cf_z17, CRSTE_1MB_WRITES, 0x0083);
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CPUMF_EVENT_ATTR(cf_z17, DTLB2_GPAGE_WRITES, 0x0084);
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CPUMF_EVENT_ATTR(cf_z17, ITLB2_WRITES, 0x0086);
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CPUMF_EVENT_ATTR(cf_z17, ITLB2_MISSES, 0x0087);
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CPUMF_EVENT_ATTR(cf_z17, TLB2_PTE_WRITES, 0x0089);
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CPUMF_EVENT_ATTR(cf_z17, TLB2_CRSTE_WRITES, 0x008a);
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CPUMF_EVENT_ATTR(cf_z17, TLB2_ENGINES_BUSY, 0x008b);
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CPUMF_EVENT_ATTR(cf_z17, TX_C_TEND, 0x008c);
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CPUMF_EVENT_ATTR(cf_z17, TX_NC_TEND, 0x008d);
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CPUMF_EVENT_ATTR(cf_z17, L1C_TLB2_MISSES, 0x008f);
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CPUMF_EVENT_ATTR(cf_z17, DCW_REQ, 0x0091);
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CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_IV, 0x0092);
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CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_CHIP_HIT, 0x0093);
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CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_DRAWER_HIT, 0x0094);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP, 0x0095);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_IV, 0x0096);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_CHIP_HIT, 0x0097);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE, 0x0099);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER, 0x009a);
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CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER, 0x009b);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_MEMORY, 0x009c);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE_MEMORY, 0x009d);
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CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER_MEMORY, 0x009e);
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CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER_MEMORY, 0x009f);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_IV, 0x00a0);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_IV, 0x00a3);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_IV, 0x00a6);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
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CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
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CPUMF_EVENT_ATTR(cf_z17, ICW_REQ, 0x00a9);
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CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_IV, 0x00aa);
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CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_CHIP_HIT, 0x00ab);
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CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_DRAWER_HIT, 0x00ac);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP, 0x00ad);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_IV, 0x00ae);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_CHIP_HIT, 0x00af);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_MODULE, 0x00b1);
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CPUMF_EVENT_ATTR(cf_z17, ICW_ON_DRAWER, 0x00b2);
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CPUMF_EVENT_ATTR(cf_z17, ICW_OFF_DRAWER, 0x00b3);
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CPUMF_EVENT_ATTR(cf_z17, CYCLES_SAMETHRD, 0x00ca);
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CPUMF_EVENT_ATTR(cf_z17, CYCLES_DIFFTHRD, 0x00cb);
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CPUMF_EVENT_ATTR(cf_z17, INST_SAMETHRD, 0x00cc);
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CPUMF_EVENT_ATTR(cf_z17, INST_DIFFTHRD, 0x00cd);
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CPUMF_EVENT_ATTR(cf_z17, WRONG_BRANCH_PREDICTION, 0x00ce);
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CPUMF_EVENT_ATTR(cf_z17, VX_BCD_EXECUTION_SLOTS, 0x00e1);
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CPUMF_EVENT_ATTR(cf_z17, DECIMAL_INSTRUCTIONS, 0x00e2);
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CPUMF_EVENT_ATTR(cf_z17, LAST_HOST_TRANSLATIONS, 0x00e8);
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CPUMF_EVENT_ATTR(cf_z17, TX_NC_TABORT, 0x00f4);
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CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_NO_SPECIAL, 0x00f5);
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CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_SPECIAL, 0x00f6);
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CPUMF_EVENT_ATTR(cf_z17, DFLT_ACCESS, 0x00f8);
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CPUMF_EVENT_ATTR(cf_z17, DFLT_CYCLES, 0x00fd);
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CPUMF_EVENT_ATTR(cf_z17, SORTL, 0x0100);
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CPUMF_EVENT_ATTR(cf_z17, DFLT_CC, 0x0109);
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CPUMF_EVENT_ATTR(cf_z17, DFLT_CCFINISH, 0x010a);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_INVOCATIONS, 0x010b);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPLETIONS, 0x010c);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_WAIT_LOCK, 0x010d);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_HOLD_LOCK, 0x010e);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_ONCHIP, 0x0110);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_OFFCHIP, 0x0111);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_DIFF, 0x0112);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_4K_PREFETCH, 0x0114);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPL_LOCK, 0x0115);
|
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CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK, 0x0116);
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CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO, 0x0117);
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CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
|
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CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
|
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|
||||
static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
|
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CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
|
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@ -414,7 +490,7 @@ static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
|
||||
static struct attribute *cpumcf_svn_678_pmu_event_attr[] __initdata = {
|
||||
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
|
||||
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
|
||||
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
|
||||
@ -779,6 +855,87 @@ static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute *cpumcf_z17_pmu_event_attr[] __initdata = {
|
||||
CPUMF_EVENT_PTR(cf_z17, L1D_RO_EXCL_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, DTLB2_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, DTLB2_MISSES),
|
||||
CPUMF_EVENT_PTR(cf_z17, CRSTE_1MB_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, DTLB2_GPAGE_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, ITLB2_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, ITLB2_MISSES),
|
||||
CPUMF_EVENT_PTR(cf_z17, TLB2_PTE_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, TLB2_CRSTE_WRITES),
|
||||
CPUMF_EVENT_PTR(cf_z17, TLB2_ENGINES_BUSY),
|
||||
CPUMF_EVENT_PTR(cf_z17, TX_C_TEND),
|
||||
CPUMF_EVENT_PTR(cf_z17, TX_NC_TEND),
|
||||
CPUMF_EVENT_PTR(cf_z17, L1C_TLB2_MISSES),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_REQ),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_MEMORY),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE_MEMORY),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER_MEMORY),
|
||||
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER_MEMORY),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_REQ),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_IV),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_CHIP_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_MODULE),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_ON_DRAWER),
|
||||
CPUMF_EVENT_PTR(cf_z17, ICW_OFF_DRAWER),
|
||||
CPUMF_EVENT_PTR(cf_z17, CYCLES_SAMETHRD),
|
||||
CPUMF_EVENT_PTR(cf_z17, CYCLES_DIFFTHRD),
|
||||
CPUMF_EVENT_PTR(cf_z17, INST_SAMETHRD),
|
||||
CPUMF_EVENT_PTR(cf_z17, INST_DIFFTHRD),
|
||||
CPUMF_EVENT_PTR(cf_z17, WRONG_BRANCH_PREDICTION),
|
||||
CPUMF_EVENT_PTR(cf_z17, VX_BCD_EXECUTION_SLOTS),
|
||||
CPUMF_EVENT_PTR(cf_z17, DECIMAL_INSTRUCTIONS),
|
||||
CPUMF_EVENT_PTR(cf_z17, LAST_HOST_TRANSLATIONS),
|
||||
CPUMF_EVENT_PTR(cf_z17, TX_NC_TABORT),
|
||||
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_NO_SPECIAL),
|
||||
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_SPECIAL),
|
||||
CPUMF_EVENT_PTR(cf_z17, DFLT_ACCESS),
|
||||
CPUMF_EVENT_PTR(cf_z17, DFLT_CYCLES),
|
||||
CPUMF_EVENT_PTR(cf_z17, SORTL),
|
||||
CPUMF_EVENT_PTR(cf_z17, DFLT_CC),
|
||||
CPUMF_EVENT_PTR(cf_z17, DFLT_CCFINISH),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_INVOCATIONS),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPLETIONS),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_WAIT_LOCK),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_HOLD_LOCK),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_ONCHIP),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_OFFCHIP),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_DIFF),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_4K_PREFETCH),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPL_LOCK),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK),
|
||||
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO),
|
||||
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
|
||||
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
|
||||
NULL,
|
||||
};
|
||||
|
||||
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
|
||||
|
||||
static struct attribute_group cpumcf_pmu_events_group = {
|
||||
@ -859,7 +1016,7 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
|
||||
if (ci.csvn >= 1 && ci.csvn <= 5)
|
||||
csvn = cpumcf_svn_12345_pmu_event_attr;
|
||||
else if (ci.csvn >= 6)
|
||||
csvn = cpumcf_svn_67_pmu_event_attr;
|
||||
csvn = cpumcf_svn_678_pmu_event_attr;
|
||||
|
||||
/* Determine model-specific counter set(s) */
|
||||
get_cpu_id(&cpu_id);
|
||||
@ -892,6 +1049,10 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
|
||||
case 0x3932:
|
||||
model = cpumcf_z16_pmu_event_attr;
|
||||
break;
|
||||
case 0x9175:
|
||||
case 0x9176:
|
||||
model = cpumcf_z17_pmu_event_attr;
|
||||
break;
|
||||
default:
|
||||
model = none;
|
||||
break;
|
||||
|
||||
@ -885,9 +885,6 @@ static int cpumsf_pmu_event_init(struct perf_event *event)
|
||||
event->attr.exclude_idle = 0;
|
||||
|
||||
err = __hw_perf_event_init(event);
|
||||
if (unlikely(err))
|
||||
if (event->destroy)
|
||||
event->destroy(event);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
@ -294,6 +294,10 @@ static int __init setup_elf_platform(void)
|
||||
case 0x3932:
|
||||
strcpy(elf_platform, "z16");
|
||||
break;
|
||||
case 0x9175:
|
||||
case 0x9176:
|
||||
strcpy(elf_platform, "z17");
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -53,6 +53,9 @@ static struct facility_def facility_defs[] = {
|
||||
#endif
|
||||
#ifdef CONFIG_HAVE_MARCH_Z15_FEATURES
|
||||
61, /* miscellaneous-instruction-extension 3 */
|
||||
#endif
|
||||
#ifdef CONFIG_HAVE_MARCH_Z17_FEATURES
|
||||
84, /* miscellaneous-instruction-extension 4 */
|
||||
#endif
|
||||
-1 /* END */
|
||||
}
|
||||
|
||||
@ -302,11 +302,17 @@ static struct airq_info *new_airq_info(int index)
|
||||
static unsigned long *get_airq_indicator(struct virtqueue *vqs[], int nvqs,
|
||||
u64 *first, void **airq_info)
|
||||
{
|
||||
int i, j;
|
||||
int i, j, queue_idx, highest_queue_idx = -1;
|
||||
struct airq_info *info;
|
||||
unsigned long *indicator_addr = NULL;
|
||||
unsigned long bit, flags;
|
||||
|
||||
/* Array entries without an actual queue pointer must be ignored. */
|
||||
for (i = 0; i < nvqs; i++) {
|
||||
if (vqs[i])
|
||||
highest_queue_idx++;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_AIRQ_AREAS && !indicator_addr; i++) {
|
||||
mutex_lock(&airq_areas_lock);
|
||||
if (!airq_areas[i])
|
||||
@ -316,7 +322,7 @@ static unsigned long *get_airq_indicator(struct virtqueue *vqs[], int nvqs,
|
||||
if (!info)
|
||||
return NULL;
|
||||
write_lock_irqsave(&info->lock, flags);
|
||||
bit = airq_iv_alloc(info->aiv, nvqs);
|
||||
bit = airq_iv_alloc(info->aiv, highest_queue_idx + 1);
|
||||
if (bit == -1UL) {
|
||||
/* Not enough vacancies. */
|
||||
write_unlock_irqrestore(&info->lock, flags);
|
||||
@ -325,8 +331,10 @@ static unsigned long *get_airq_indicator(struct virtqueue *vqs[], int nvqs,
|
||||
*first = bit;
|
||||
*airq_info = info;
|
||||
indicator_addr = info->aiv->vector;
|
||||
for (j = 0; j < nvqs; j++) {
|
||||
airq_iv_set_ptr(info->aiv, bit + j,
|
||||
for (j = 0, queue_idx = 0; j < nvqs; j++) {
|
||||
if (!vqs[j])
|
||||
continue;
|
||||
airq_iv_set_ptr(info->aiv, bit + queue_idx++,
|
||||
(unsigned long)vqs[j]);
|
||||
}
|
||||
write_unlock_irqrestore(&info->lock, flags);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user