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mfd: tps65219: Add support for TI TPS65214 PMIC
Use chip ID and chip_data struct to differentiate between 3 PMIC devices in probe(). Add TPS65214 resource information. Update descriptions and copyright information to reflect the driver supports 3 PMIC devices. Signed-off-by: Shree Ramamoorthy <s-ramamoorthy@ti.com> Link: https://lore.kernel.org/r/20250206173725.386720-6-s-ramamoorthy@ti.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Shree Ramamoorthy
Lee Jones
parent
7f9ed27eea
commit
7947219ab1
@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC)
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// Driver for TPS65214/TPS65215/TPS65219 Power Management Integrated Chips
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//
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// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
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// Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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@ -60,6 +60,44 @@ static const struct resource tps65219_pwrbutton_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"),
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};
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static const struct resource tps65214_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO2_RV, "LDO2_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO1_RV_SD, "LDO1_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
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};
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static const struct resource tps65215_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"),
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@ -150,6 +188,11 @@ static const struct resource tps65219_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
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};
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static const struct mfd_cell tps65214_cells[] = {
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MFD_CELL_RES("tps65214-regulator", tps65214_regulator_resources),
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MFD_CELL_NAME("tps65215-gpio"),
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};
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static const struct mfd_cell tps65215_cells[] = {
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MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources),
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MFD_CELL_NAME("tps65215-gpio"),
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@ -186,6 +229,15 @@ static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS };
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static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS };
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static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */
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/* TPS65214 INT_SOURCE bit 6 is 'RESERVED'*/
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static unsigned int tps65214_bit0_offsets[] = { TPS65214_REG_INT_TO_RV_POS };
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static unsigned int tps65214_bit1_offsets[] = { TPS65214_REG_INT_RV_POS };
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static unsigned int tps65214_bit2_offsets[] = { TPS65214_REG_INT_SYS_POS };
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static unsigned int tps65214_bit3_offsets[] = { TPS65214_REG_INT_BUCK_1_2_POS };
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static unsigned int tps65214_bit4_offsets[] = { TPS65214_REG_INT_BUCK_3_POS };
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static unsigned int tps65214_bit5_offsets[] = { TPS65214_REG_INT_LDO_1_2_POS };
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static unsigned int tps65214_bit7_offsets[] = { TPS65214_REG_INT_PB_POS };
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static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
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@ -208,9 +260,59 @@ static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
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};
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static struct regmap_irq_sub_irq_map tps65214_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit1_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit2_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit3_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit4_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit5_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit7_offsets),
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};
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#define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \
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REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)
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static const struct regmap_irq tps65214_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65214_REG_INT_LDO_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65214_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65214_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65214_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65214_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65214_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65214_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65214_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65214_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65214_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65214_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO2_RV, TPS65214_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO1_RV_SD, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65214_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65214_REG_INT_PB_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65214_REG_INT_PB_POS),
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};
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static const struct regmap_irq tps65215_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS),
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@ -305,6 +407,20 @@ static const struct regmap_irq tps65219_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
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};
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static const struct regmap_irq_chip tps65214_irq_chip = {
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.name = "tps65214_irq",
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.main_status = TPS65219_REG_INT_SOURCE,
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.num_main_regs = 1,
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.num_main_status_bits = 8,
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.irqs = tps65214_irqs,
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.num_irqs = ARRAY_SIZE(tps65214_irqs),
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.status_base = TPS65214_REG_INT_LDO_1_2,
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.ack_base = TPS65214_REG_INT_LDO_1_2,
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.clear_ack = 1,
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.num_regs = 8,
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.sub_reg_offsets = tps65214_sub_irq_offsets,
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};
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static const struct regmap_irq_chip tps65215_irq_chip = {
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.name = "tps65215_irq",
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.main_status = TPS65219_REG_INT_SOURCE,
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@ -340,6 +456,11 @@ struct tps65219_chip_data {
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};
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static struct tps65219_chip_data chip_info_table[] = {
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[TPS65214] = {
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.irq_chip = &tps65214_irq_chip,
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.cells = tps65214_cells,
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.n_cells = ARRAY_SIZE(tps65214_cells),
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},
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[TPS65215] = {
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.irq_chip = &tps65215_irq_chip,
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.cells = tps65215_cells,
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@ -421,6 +542,7 @@ static int tps65219_probe(struct i2c_client *client)
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}
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static const struct of_device_id of_tps65219_match_table[] = {
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{ .compatible = "ti,tps65214", .data = (void *)TPS65214, },
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{ .compatible = "ti,tps65215", .data = (void *)TPS65215, },
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{ .compatible = "ti,tps65219", .data = (void *)TPS65219, },
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{}
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@ -437,5 +559,5 @@ static struct i2c_driver tps65219_driver = {
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module_i2c_driver(tps65219_driver);
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MODULE_AUTHOR("Jerome Neanne <jneanne@baylibre.com>");
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MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver");
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MODULE_DESCRIPTION("TPS65214/TPS65215/TPS65219 PMIC driver");
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MODULE_LICENSE("GPL");
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@ -16,6 +16,7 @@
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/* Chip id list*/
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enum pmic_id {
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TPS65214,
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TPS65215,
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TPS65219,
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};
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@ -28,17 +29,23 @@ enum pmic_id {
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#define TPS65219_REG_NVM_ID 0x01
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#define TPS65219_REG_ENABLE_CTRL 0x02
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#define TPS65219_REG_BUCKS_CONFIG 0x03
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#define TPS65214_REG_LOCK 0x03
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#define TPS65219_REG_LDO4_VOUT 0x04
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#define TPS65214_REG_LDO1_VOUT_STBY 0x04
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#define TPS65219_REG_LDO3_VOUT 0x05
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#define TPS65215_REG_LDO2_VOUT 0x05
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#define TPS65214_REG_LDO1_VOUT 0x05
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#define TPS65219_REG_LDO2_VOUT 0x06
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#define TPS65214_REG_LDO2_VOUT 0x06
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#define TPS65219_REG_LDO1_VOUT 0x07
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#define TPS65214_REG_LDO2_VOUT_STBY 0x07
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#define TPS65219_REG_BUCK3_VOUT 0x8
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#define TPS65219_REG_BUCK2_VOUT 0x9
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#define TPS65219_REG_BUCK1_VOUT 0xA
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#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
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#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
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#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC
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#define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC
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#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
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#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
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#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
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@ -47,15 +54,21 @@ enum pmic_id {
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#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12
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#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13
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#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14
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#define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14
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#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15
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#define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17
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/* _SLOT_DURATION_3 doesn't apply to TPS65215*/
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19
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#define TPS65214_REG_BUCK3_VOUT_STBY 0x19
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C
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#define TPS65214_REG_BUCK2_VOUT_STBY 0x1C
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D
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#define TPS65214_REG_BUCK1_VOUT_STBY 0x1D
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#define TPS65219_REG_GENERAL_CONFIG 0x1E
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#define TPS65219_REG_MFP_1_CONFIG 0x1F
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#define TPS65219_REG_MFP_2_CONFIG 0x20
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@ -82,6 +95,9 @@ enum pmic_id {
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#define TPS65215_REG_INT_LDO_2 0x2C
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#define TPS65215_REG_INT_LDO_1 0x2D
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/* TPS65214 specific 'sub irq' register */
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#define TPS65214_REG_INT_LDO_1_2 0x2D
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/* Common TPS65215 & TPS65219 'sub irq' registers */
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#define TPS65219_REG_INT_BUCK_3 0x2E
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#define TPS65219_REG_INT_BUCK_1_2 0x2F
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@ -102,6 +118,14 @@ enum pmic_id {
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#define TPS65215_REG_INT_LDO_2_POS 0
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#define TPS65215_REG_INT_LDO_1_POS 1
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||||
#define TPS65214_REG_INT_LDO_1_2_POS 0
|
||||
#define TPS65214_REG_INT_BUCK_3_POS 1
|
||||
#define TPS65214_REG_INT_BUCK_1_2_POS 2
|
||||
#define TPS65214_REG_INT_SYS_POS 3
|
||||
#define TPS65214_REG_INT_RV_POS 4
|
||||
#define TPS65214_REG_INT_TO_RV_POS 5
|
||||
#define TPS65214_REG_INT_PB_POS 6
|
||||
|
||||
#define TPS65219_REG_USER_NVM_CMD 0x34
|
||||
#define TPS65219_REG_POWER_UP_STATUS 0x35
|
||||
#define TPS65219_REG_SPARE_2 0x36
|
||||
@ -124,6 +148,7 @@ enum pmic_id {
|
||||
#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
|
||||
#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
|
||||
#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5)
|
||||
#define TPS65214_ENABLE_LDO1_EN_MASK BIT(5)
|
||||
#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
|
||||
/* power ON-OFF sequence slot */
|
||||
#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
|
||||
@ -175,14 +200,14 @@ enum pmic_id {
|
||||
#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
|
||||
#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
|
||||
/* UnderVoltage - Short to GND - OverCurrent*/
|
||||
/* LDO3-4 */
|
||||
/* LDO3-4: only for TPS65219*/
|
||||
#define TPS65219_INT_LDO3_SCG_MASK BIT(0)
|
||||
#define TPS65219_INT_LDO3_OC_MASK BIT(1)
|
||||
#define TPS65219_INT_LDO3_UV_MASK BIT(2)
|
||||
#define TPS65219_INT_LDO4_SCG_MASK BIT(3)
|
||||
#define TPS65219_INT_LDO4_OC_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO4_UV_MASK BIT(5)
|
||||
/* LDO1-2 */
|
||||
/* LDO1-2: TPS65214 & TPS65219 */
|
||||
#define TPS65219_INT_LDO1_SCG_MASK BIT(0)
|
||||
#define TPS65219_INT_LDO1_OC_MASK BIT(1)
|
||||
#define TPS65219_INT_LDO1_UV_MASK BIT(2)
|
||||
@ -210,12 +235,13 @@ enum pmic_id {
|
||||
#define TPS65219_INT_BUCK2_OC_MASK BIT(5)
|
||||
#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
|
||||
#define TPS65219_INT_BUCK2_UV_MASK BIT(7)
|
||||
/* Thermal Sensor */
|
||||
/* Thermal Sensor: TPS65219/TPS65215 */
|
||||
#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
|
||||
#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
|
||||
/* Thermal Sensor: TPS65219/TPS65215/TPS65214 */
|
||||
#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
|
||||
#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
|
||||
#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
|
||||
#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
|
||||
#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
|
||||
#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
|
||||
#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
|
||||
@ -227,6 +253,7 @@ enum pmic_id {
|
||||
#define TPS65219_INT_LDO2_RV_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO3_RV_MASK BIT(5)
|
||||
#define TPS65215_INT_LDO2_RV_MASK BIT(5)
|
||||
#define TPS65214_INT_LDO2_RV_MASK BIT(5)
|
||||
#define TPS65219_INT_LDO4_RV_MASK BIT(6)
|
||||
/* Residual Voltage ShutDown */
|
||||
#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
|
||||
@ -236,6 +263,7 @@ enum pmic_id {
|
||||
#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
|
||||
#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5)
|
||||
#define TPS65214_INT_LDO1_RV_SD_MASK BIT(5)
|
||||
#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
|
||||
#define TPS65219_INT_TIMEOUT_MASK BIT(7)
|
||||
/* Power Button */
|
||||
@ -269,7 +297,7 @@ enum {
|
||||
TPS65215_INT_LDO2_SCG,
|
||||
TPS65215_INT_LDO2_OC,
|
||||
TPS65215_INT_LDO2_UV,
|
||||
/* LDO1-2 */
|
||||
/* LDO1-2: TPS65219/TPS65214 */
|
||||
TPS65219_INT_LDO1_SCG,
|
||||
TPS65219_INT_LDO1_OC,
|
||||
TPS65219_INT_LDO1_UV,
|
||||
@ -306,6 +334,7 @@ enum {
|
||||
TPS65219_INT_LDO1_RV,
|
||||
TPS65219_INT_LDO2_RV,
|
||||
TPS65215_INT_LDO2_RV,
|
||||
TPS65214_INT_LDO2_RV,
|
||||
TPS65219_INT_LDO3_RV,
|
||||
TPS65219_INT_LDO4_RV,
|
||||
/* Residual Voltage ShutDown */
|
||||
@ -313,6 +342,7 @@ enum {
|
||||
TPS65219_INT_BUCK2_RV_SD,
|
||||
TPS65219_INT_BUCK3_RV_SD,
|
||||
TPS65219_INT_LDO1_RV_SD,
|
||||
TPS65214_INT_LDO1_RV_SD,
|
||||
TPS65215_INT_LDO2_RV_SD,
|
||||
TPS65219_INT_LDO2_RV_SD,
|
||||
TPS65219_INT_LDO3_RV_SD,
|
||||
@ -323,6 +353,17 @@ enum {
|
||||
TPS65219_INT_PB_RISING_EDGE_DETECT,
|
||||
};
|
||||
|
||||
enum tps65214_regulator_id {
|
||||
/*
|
||||
* DCDC's same as TPS65219
|
||||
* LDO1 maps to TPS65219's LDO3
|
||||
* LDO2 is the same as TPS65219
|
||||
*
|
||||
*/
|
||||
TPS65214_LDO_1 = 3,
|
||||
TPS65214_LDO_2 = 4,
|
||||
};
|
||||
|
||||
enum tps65215_regulator_id {
|
||||
/* DCDC's same as TPS65219 */
|
||||
/* LDO1 is the same as TPS65219 */
|
||||
@ -346,9 +387,23 @@ enum tps65219_regulator_id {
|
||||
/* Number of LDO voltage regulators available */
|
||||
#define TPS65219_NUM_LDO 4
|
||||
#define TPS65215_NUM_LDO 2
|
||||
#define TPS65214_NUM_LDO 2
|
||||
/* Number of total regulators available */
|
||||
#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO)
|
||||
#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO)
|
||||
#define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO)
|
||||
|
||||
/* Define the TPS65214 IRQ numbers */
|
||||
enum tps65214_irqs {
|
||||
/* INT source registers */
|
||||
TPS65214_TO_RV_SD_SET_IRQ,
|
||||
TPS65214_RV_SET_IRQ,
|
||||
TPS65214_SYS_SET_IRQ,
|
||||
TPS65214_BUCK_1_2_SET_IRQ,
|
||||
TPS65214_BUCK_3_SET_IRQ,
|
||||
TPS65214_LDO_1_2_SET_IRQ,
|
||||
TPS65214_PB_SET_IRQ = 7,
|
||||
};
|
||||
|
||||
/* Define the TPS65215 IRQ numbers */
|
||||
enum tps65215_irqs {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user