mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/
synced 2025-04-19 20:58:31 +09:00
Merge branch 'kvm-arm64/pmu-fixes' into kvmarm/next
* kvm-arm64/pmu-fixes:
: vPMU fixes for 6.15 courtesy of Akihiko Odaki
:
: Various fixes to KVM's vPMU implementation, notably ensuring
: userspace-directed changes to the PMCs are reflected in the backing perf
: events.
KVM: arm64: PMU: Reload when resetting
KVM: arm64: PMU: Reload when user modifies registers
KVM: arm64: PMU: Fix SET_ONE_REG for vPMC regs
KVM: arm64: PMU: Assume PMU presence in pmu-emul.c
KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Oliver Upton
commit
369c012268
@ -858,9 +858,11 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
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if (ret)
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return ret;
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ret = kvm_arm_pmu_v3_enable(vcpu);
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if (ret)
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return ret;
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if (kvm_vcpu_has_pmu(vcpu)) {
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ret = kvm_arm_pmu_v3_enable(vcpu);
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if (ret)
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return ret;
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}
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if (is_protected_kvm_enabled()) {
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ret = pkvm_create_hyp_vm(kvm);
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@ -1175,7 +1177,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
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*/
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preempt_disable();
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kvm_pmu_flush_hwstate(vcpu);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_pmu_flush_hwstate(vcpu);
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local_irq_disable();
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@ -1194,7 +1197,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
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if (ret <= 0 || kvm_vcpu_exit_request(vcpu, &ret)) {
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vcpu->mode = OUTSIDE_GUEST_MODE;
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isb(); /* Ensure work in x_flush_hwstate is committed */
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kvm_pmu_sync_hwstate(vcpu);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_pmu_sync_hwstate(vcpu);
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if (unlikely(!irqchip_in_kernel(vcpu->kvm)))
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kvm_timer_sync_user(vcpu);
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kvm_vgic_sync_hwstate(vcpu);
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@ -1224,7 +1228,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
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* that the vgic can properly sample the updated state of the
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* interrupt line.
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*/
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kvm_pmu_sync_hwstate(vcpu);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_pmu_sync_hwstate(vcpu);
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/*
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* Sync the vgic state before syncing the timer state because
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@ -2518,7 +2518,8 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
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vcpu_clear_flag(vcpu, IN_NESTED_ERET);
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preempt_enable();
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kvm_pmu_nested_transition(vcpu);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_pmu_nested_transition(vcpu);
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}
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static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
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@ -2601,7 +2602,8 @@ static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2,
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kvm_arch_vcpu_load(vcpu, smp_processor_id());
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preempt_enable();
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kvm_pmu_nested_transition(vcpu);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_pmu_nested_transition(vcpu);
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return 1;
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}
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@ -154,9 +154,6 @@ static u64 kvm_pmu_get_pmc_value(struct kvm_pmc *pmc)
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*/
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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return kvm_pmu_get_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx));
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}
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@ -195,12 +192,22 @@ static void kvm_pmu_set_pmc_value(struct kvm_pmc *pmc, u64 val, bool force)
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*/
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
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{
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx), val, false);
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}
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/**
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* kvm_pmu_set_counter_value_user - set PMU counter value from user
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* @vcpu: The vcpu pointer
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* @select_idx: The counter index
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* @val: The counter value
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*/
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void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
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{
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kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, select_idx));
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__vcpu_sys_reg(vcpu, counter_index_to_reg(select_idx)) = val;
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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}
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/**
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* kvm_pmu_release_perf_event - remove the perf event
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* @pmc: The PMU counter pointer
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@ -251,20 +258,6 @@ void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu)
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pmu->pmc[i].idx = i;
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}
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/**
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* kvm_pmu_vcpu_reset - reset pmu state for cpu
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* @vcpu: The vcpu pointer
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*
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*/
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void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
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{
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unsigned long mask = kvm_pmu_implemented_counter_mask(vcpu);
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int i;
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for_each_set_bit(i, &mask, 32)
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kvm_pmu_stop_counter(kvm_vcpu_idx_to_pmc(vcpu, i));
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}
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/**
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* kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
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* @vcpu: The vcpu pointer
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@ -354,7 +347,7 @@ void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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if (!kvm_vcpu_has_pmu(vcpu) || !val)
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if (!val)
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return;
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for (i = 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) {
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@ -405,9 +398,6 @@ static void kvm_pmu_update_state(struct kvm_vcpu *vcpu)
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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bool overflow;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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overflow = kvm_pmu_overflow_status(vcpu);
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if (pmu->irq_level == overflow)
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return;
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@ -603,9 +593,6 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
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{
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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/* Fixup PMCR_EL0 to reconcile the PMU version and the LP bit */
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if (!kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5))
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val &= ~ARMV8_PMU_PMCR_LP;
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@ -793,9 +780,6 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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struct kvm_pmc *pmc = kvm_vcpu_idx_to_pmc(vcpu, select_idx);
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u64 reg;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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reg = counter_index_to_evtreg(pmc->idx);
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__vcpu_sys_reg(vcpu, reg) = data & kvm_pmu_evtyper_mask(vcpu->kvm);
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@ -901,9 +885,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
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u64 val, mask = 0;
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int base, i, nr_events;
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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if (!pmceid1) {
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val = compute_pmceid0(cpu_pmu);
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base = 0;
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@ -944,9 +925,6 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu)
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int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
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{
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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if (!vcpu->arch.pmu.created)
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return -EINVAL;
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@ -969,9 +947,6 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
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return -EINVAL;
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}
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/* One-off reload of the PMU on first run */
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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return 0;
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}
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@ -1295,9 +1270,6 @@ void kvm_pmu_nested_transition(struct kvm_vcpu *vcpu)
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unsigned long mask;
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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mask = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
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for_each_set_bit(i, &mask, 32) {
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struct kvm_pmc *pmc = kvm_vcpu_idx_to_pmc(vcpu, i);
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@ -196,9 +196,6 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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vcpu->arch.reset_state.reset = false;
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spin_unlock(&vcpu->arch.mp_state_lock);
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/* Reset PMU outside of the non-preemptible section */
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kvm_pmu_vcpu_reset(vcpu);
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preempt_disable();
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loaded = (vcpu->cpu != -1);
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if (loaded)
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@ -967,6 +967,22 @@ static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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return 0;
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}
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static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u64 idx;
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if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
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/* PMCCNTR_EL0 */
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idx = ARMV8_PMU_CYCLE_IDX;
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else
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/* PMEVCNTRn_EL0 */
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idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
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kvm_pmu_set_counter_value_user(vcpu, idx, val);
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return 0;
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}
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static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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@ -1058,25 +1074,10 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
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{
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bool set;
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u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
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val &= kvm_pmu_accessible_counter_mask(vcpu);
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switch (r->reg) {
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case PMOVSSET_EL0:
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/* CRm[1] being set indicates a SET register, and CLR otherwise */
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set = r->CRm & 2;
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break;
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default:
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/* Op2[0] being set indicates a SET register, and CLR otherwise */
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set = r->Op2 & 1;
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break;
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}
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if (set)
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__vcpu_sys_reg(vcpu, r->reg) |= val;
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else
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__vcpu_sys_reg(vcpu, r->reg) &= ~val;
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__vcpu_sys_reg(vcpu, r->reg) = val & mask;
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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return 0;
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}
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@ -1236,6 +1237,8 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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val |= ARMV8_PMU_PMCR_LC;
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__vcpu_sys_reg(vcpu, r->reg) = val;
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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return 0;
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}
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@ -1262,6 +1265,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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#define PMU_PMEVCNTR_EL0(n) \
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{ PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
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.reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
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.set_user = set_pmu_evcntr, \
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.access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
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/* Macro to expand the PMEVTYPERn_EL0 register */
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@ -1880,12 +1884,14 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
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static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
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u8 perfmon;
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u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
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val &= ~ID_DFR0_EL1_PerfMon_MASK;
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if (kvm_vcpu_has_pmu(vcpu))
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if (kvm_vcpu_has_pmu(vcpu)) {
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perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
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val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
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}
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val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
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@ -3052,7 +3058,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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.access = access_pmceid, .reset = NULL },
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{ PMU_SYS_REG(PMCCNTR_EL0),
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.access = access_pmu_evcntr, .reset = reset_unknown,
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.reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
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.reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr,
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.set_user = set_pmu_evcntr },
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{ PMU_SYS_REG(PMXEVTYPER_EL0),
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.access = access_pmu_evtyper, .reset = NULL },
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{ PMU_SYS_REG(PMXEVCNTR_EL0),
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@ -4712,6 +4719,9 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
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}
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set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
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if (kvm_vcpu_has_pmu(vcpu))
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kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
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}
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/**
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@ -41,11 +41,11 @@ bool kvm_supports_guest_pmuv3(void);
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#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu);
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u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu);
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u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);
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void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
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void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
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@ -109,6 +109,8 @@ static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
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}
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static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx, u64 val) {}
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static inline void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu,
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u64 select_idx, u64 val) {}
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static inline u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu)
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{
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return 0;
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@ -118,7 +120,6 @@ static inline u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)
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return 0;
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}
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static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
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