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dt-bindings: xilinx: Remove myself from maintainership
As I am leaving AMD and will no longer be maintaining these platform drivers, so removing myself from maintainership. Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com> Acked-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250403060836.2602361-1-mubin.sayyed@amd.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Ceva AHCI SATA Controller
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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description: |
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@ -12,7 +12,6 @@ description:
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PS_MODE). Every pin can be configured as input/output.
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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properties:
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@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Zynq UltraScale+ MPSoC and Versal reset
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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description: |
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@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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properties:
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@ -17,7 +17,6 @@ description:
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maintainers:
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- Michal Simek <michal.simek@amd.com>
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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properties:
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@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx udc controller
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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properties:
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